Dual-path phase-locked loop
AssigneeNXP USA, Inc.
InventorsSaurabh Goyal, Anand Kumar Sinha, Ateet Omer
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Abstract
A dual-path phase-locked loop (PLL) is disclosed. The dual-path PLL converts, based on a masking value, a pulse signal to a masked pulse signal such that the masked pulse signal comprises one or more unmasked pulses and one or more masked pulses of the pulse signal. An integral current is generated, based on the masked pulse signal in a manner such that that an average current value of the integral current reaches a desired value over a predefined number of cycles of the pulse signal and an optimal peaking in the dual-path PLL is achieved.
Claims20
A dual-path phase-locked loop (PLL), comprising:
- a phase-frequency detector configured to output a pulse signal;
- a pulse masking circuit coupled to the phase-frequency detector, wherein the pulse masking circuit is configured to convert, based on a masking value, the pulse signal to a masked pulse signal such that the masked pulse signal comprises one or more unmasked pulses and one or more masked pulses;
- and
- an integral charge pump coupled to the pulse masking circuit, wherein the integral charge pump is configured to generate, based on the masked pulse signal, an integral current.
A method comprising:
- outputting, by a phase-frequency detector of a dual-path phase-locked loop (PLL), a pulse signal;
- converting, by a pulse masking circuit of the dual-path PLL, the pulse signal to a masked pulse signal based on a masking value, wherein the masked pulse signal comprises one or more unmasked pulses and one or more masked pulses;
- and
- generating, by an integral charge pump of the dual-path PLL based on the masked pulse signal.
Dependencies are inferred from the claim text.