H03K 19/01728
In synchronous circuits, i.e. by using clock signals
Official title: {in synchronous circuits, i.e. by using clock signals}
H03K19/01728 (In synchronous circuits, i.e. by using clock signals) appears on 351 US grants and 206 published applications in this corpus.
Search patents in H03K- Granted patents
- 351
- Published applications
- 206
- Assignees
- 164
- Inventors
- 619
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 4 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 4 | 0 |
| 1982 | 3 | 0 |
| 1983 | 7 | 0 |
| 1984 | 6 | 0 |
| 1985 | 7 | 0 |
| 1986 | 11 | 0 |
| 1987 | 10 | 0 |
| 1988 | 2 | 0 |
| 1989 | 4 | 0 |
| 1990 | 7 | 0 |
| 1991 | 7 | 0 |
| 1992 | 7 | 0 |
| 1993 | 1 | 0 |
| 1994 | 6 | 0 |
| 1995 | 5 | 0 |
| 1996 | 10 | 0 |
| 1997 | 8 | 0 |
| 1998 | 4 | 0 |
| 1999 | 7 | 0 |
| 2000 | 5 | 0 |
| 2001 | 8 | 3 |
| 2002 | 7 | 5 |
| 2003 | 6 | 8 |
| 2004 | 9 | 10 |
| 2005 | 4 | 3 |
| 2006 | 8 | 4 |
| 2007 | 2 | 4 |
| 2008 | 5 | 5 |
| 2009 | 4 | 3 |
| 2010 | 3 | 3 |
| 2011 | 7 | 5 |
| 2012 | 3 | 2 |
| 2013 | 5 | 4 |
| 2014 | 6 | 3 |
| 2015 | 3 | 1 |
| 2016 | 3 | 5 |
| 2017 | 6 | 5 |
| 2018 | 5 | 6 |
| 2019 | 6 | 4 |
| 2020 | 10 | 11 |
| 2021 | 11 | 11 |
| 2022 | 15 | 35 |
| 2023 | 19 | 27 |
| 2024 | 33 | 21 |
| 2025 | 23 | 12 |
| 2026 | 9 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Memory device6 Oct 2026US 12,755,773 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Storage device including pad for determining link startup mode and method of controlling level of pad for determining link startup mode thereof6 Oct 2026US 12,756,395 B2Samsung Electronics Co., Ltd.
- Bootstrapped switch circuit1 Sep 2026US 12,726,193 B2Realtek Semiconductor Corp.
- Data read circuit and storage device thereof11 Aug 2026US 12,706,138 B2CXMT Corporation
- Shared clock dual edge-triggered flip-flop circuit23 Jun 2026US 12,665,600 B2Intel Corporation
- Memory device, memory system, and operating method of input/output circuit6 Aug 2026US 2026/0229280 A1Yangtze Memory Technologies Co., Ltd.
- Latch-Based Low-Density Parity Check (LDPC) Implementations2 Jul 2026US 2026/0186893 A1SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Delay circuit and memory device including the same18 Jun 2026US 2026/0171128 A1SK hynix Inc.
- Digital Display Control Buffer Circuit and Digital Display Control Buffer Apparatus11 Jun 2026US 2026/0162627 A1Analogix International LLC
- Data input/output circuit and memory9 Apr 2026US 2026/0100207 A1CXMT Corporation
Most cited
By later US patents
- Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same188US 9,621,173 B12017
- Bootstrap circuit suitable for buffer circuit or shift register circuit157US 5,949,271 ANEC Corporation · 1999
- System for interconnecting VLSI circuits with transmission line characteristics142US 5,347,177 A1994
- Pulse output circuit, shift register, and display device129US 6,928,136 B2Semiconductor Energy Laboratory Co.Ltd. · 2005
- Bootstrap type output circuit75US 4,633,105 ANEC Corporation · 1986