Data input/output circuit and memory

A data input/output circuit, comprising a parallel-to-serial conversion circuit, a read enable signal generation circuit, a resistance control circuit, and an output drive circuit, wherein

• the parallel-to-serial conversion circuit is configured to receive N pieces of data, and serially output the N pieces of data in a first time period;
• the read enable signal generation circuit is configured to generate a read enable signal, and the read enable signal is at an active level in the first time period;
• the resistance control circuit is electrically connected to the read enable signal generation circuit, and is configured to receive a termination resistance control code, an output drive resistance control code, and the read enable signal, and choose, based on the read enable signal, to output the termination resistance control code or output the output drive resistance control code;
• and
• the output drive circuit is electrically connected to the parallel-to-serial conversion circuit and the resistance control circuit, and is configured to receive the N pieces of data and a signal output by the resistance control circuit, configure an output drive resistance value based on the signal output by the resistance control circuit and output the N pieces of data, or configure a termination resistance value,
• wherein N is a positive integer greater than 1.