Memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShigeki Shimomura, Jonathan Tsung-Yung Chang
Life of this patent
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Abstract
A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.
Claims20
A memory device, comprising:
- a memory cell array comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line, and wherein each of the first plurality of memory cells comprising:
- a first invertor connected between a first node and a second node, and
- a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node;
- a pull down line, wherein the second node of each of the first plurality of memory cells is connected to the pull down line;
- and
- a pull down circuit connected to the pull down line, wherein the pull down circuit is operative to pull down a voltage of the second node through the pull down line to below a ground voltage in response to receiving an enable signal, wherein the enable signal is activated before a word line activation signal, the word line activation signal indicating a write operation on the memory device.
A memory device, comprising:
- a memory cell array comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of rows comprises a first plurality of memory cells connected to a first bit line and a second bit line, and wherein each of the first plurality of memory cells comprising:
- a first invertor connected between a first node and a second node, and
- a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node;
- a pull down line, wherein the second node of each of the first plurality of memory cells is connected to the pull down line;
- a pull down circuit connected to the pull down line, wherein the pull down circuit is operative to pull down a voltage of the second node through the pull down line to below a ground voltage in response to receiving an enable signal, wherein the enable signal is activated before a word line activation signal, the word line activation signal indicating a write operation on the memory device.
A memory device, comprising:
- a bit cell comprising:
- a first invertor connected between a first node and a second node, and
- a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node;
- a write driver connected to each of a first bit line and a second bit line;
- and
- a pull down circuit connected to both the second node and a ground node of the write driver circuit, wherein the pull down circuit is operative to pull down a voltage of the second node and the ground node of the write driver to below a ground voltage in response to receiving a write enable signal.
Dependencies are inferred from the claim text.