Delay circuit and memory device including the same

A delay circuit comprising:

• a pull-up driver operating according to an input signal and coupled between a supply terminal of a high voltage and a compensation control terminal;
• a pull-down driver operating according to the input signal and coupled between a supply terminal of a low voltage and a coupling node;
• and
• a compensation driver operating according to a voltage level of a single control signal and coupled between the coupling node and the compensation control terminal.

A memory device comprising:

• a sense amplification circuit configured to sense and amplify data loaded on a pair of bit lines;
• a delay circuit configured to adjust a deactivation point in time of a compensation control signal based on an input signal and a control signal depending on parameters;
• and
• a compensation circuit configured to differentially compensate for a mismatch of the sense amplification circuit based on the compensation control signal.