Shared clock dual edge-triggered flip-flop circuit

An apparatus comprising:

• a multiplexer including a first input node to receive data information and a second input node to receive scan information;
• a first tristate inverter including an input node to receive information based on one of the data information and scan information selected by the multiplexer;
• a second tristate inverter including an input node coupled to the input node of the first tristate inverter;
• a first additional tristate inverter including an input node and an output node;
• a second additional tristate inverter including an input node and an output node coupled to the output node of the first additional tristate inverter;
• a first memory including an inverter coupled between an output node of the second tristate inverter and the input node of the first additional tristate inverter;
• and
• a second memory including an inverter coupled between an output node of the first tristate inverter and the input node of the second additional tristate inverter.

A method comprising:

• providing data information to an input stage of a scan flip-flop circuit;
• storing the data information in a first memory node and a second memory node of a memory of the scan flip-flop circuit;
• and
• providing data information from the second memory node to an input node of an output stage of the flip-flop circuit, wherein the input stage includes a first tristate inverter and the output stage includes a second tristate inverter, the first and second tristate inverters sharing a transistor, and the input node of the output stage is separated from the first memory node by an inverter.