Memory device, memory system, and operating method of input/output circuit

A memory system, comprising:

• at least one memory device, the memory device comprising:
• a first die, comprising:
• an impedance calibration circuit, comprising:
• a receiving circuit,
• a transmitting circuit, and
• a calibration control circuit, wherein
• the receiving circuit is coupled with the calibration control circuit and is configured to generate a calibration start signal;
• the calibration control circuit is configured to generate a first enable signal based on the calibration start signal, and generate a second enable signal after generating the first enable signal;
• the transmitting circuit is coupled with the calibration control circuit and is configured to output a third enable signal based on the second enable signal;
• and
• the receiving circuit is further configured to generate a first calibration end signal;
• and
• a controller coupled with the at least one memory device and configured to control the memory device.

An operating method of an input/output circuit, comprising:

• generating a calibration start signal;
• generating a first enable signal based on the calibration start signal, and generating a second enable signal after generating the first enable signal;
• outputting a third enable signal based on the second enable signal;
• and
• generating a first calibration end signal.