G11C 2211/5622
Concurrent multilevel programming of more than one cell
G11C2211/5622 (Concurrent multilevel programming of more than one cell) appears on 130 US grants and 102 published applications in this corpus.
Search patents in G11C- Granted patents
- 130
- Published applications
- 102
- Assignees
- 40
- Inventors
- 208
- Latest grant
- 18 Feb 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 4 | 0 |
| 1997 | 2 | 0 |
| 1998 | 6 | 0 |
| 1999 | 1 | 0 |
| 2000 | 2 | 0 |
| 2001 | 2 | 0 |
| 2002 | 2 | 1 |
| 2003 | 2 | 0 |
| 2004 | 1 | 1 |
| 2005 | 1 | 0 |
| 2006 | 2 | 1 |
| 2007 | 0 | 3 |
| 2008 | 4 | 7 |
| 2009 | 2 | 6 |
| 2010 | 9 | 7 |
| 2011 | 6 | 4 |
| 2012 | 5 | 1 |
| 2013 | 3 | 3 |
| 2014 | 3 | 3 |
| 2015 | 4 | 3 |
| 2016 | 6 | 7 |
| 2017 | 7 | 10 |
| 2018 | 11 | 4 |
| 2019 | 7 | 8 |
| 2020 | 8 | 10 |
| 2021 | 5 | 6 |
| 2022 | 7 | 8 |
| 2023 | 7 | 5 |
| 2024 | 6 | 3 |
| 2025 | 2 | 0 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Dynamic program caching18 Feb 2025US 12,230,334 B2Intel NDTM US LLC
- Skip program verify for dynamic start voltage sampling7 Jan 2025US 12,189,955 B2Intel NDTM US LLC
- Nonvolatile memory device including selection transistors and operating method thereof17 Dec 2024US 12,170,111 B2SK hynix Inc.
- Method for programming memory device to reduce retention error9 Jul 2024US 12,033,708 B2Yangtze Memory Technologies Co., Ltd.
- Apparatus and method for programming data in a non-volatile memory device21 May 2024US 11,990,191 B2SK hynix Inc.
- Padding memory by programming user data in parallel5 Feb 2026US 2026/0037421 A1Micron Technology, Inc.
- Two-part programming of memory cells6 Jun 2024US 2024/0185923 A1Lodestar Licensing Group LLC
- Simultaneous statistical multi-subblock verify for nand memories25 Apr 2024US 2024/0136002 A1Intel NDTM US LLC
- Nonvolatile memory device including selection transistors and operating method thereof11 Apr 2024US 2024/0120008 A1SK hynix Inc.
- Dynamic program caching5 Oct 2023US 2023/0317182 A1Intel NDTM US LLC
Most cited
By later US patents
- Operation of a non-volatile memory array458US 7,924,628 B2Spansion Israel Ltd · 2011
- Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells221US 5,712,815 AAdvanced Micro Devices, Inc. · 1998
- Memory with isolatable expandable bit lines211US 5,677,867 A1997
- Bit line discharge method for reading a multiple bits-per-cell flash EEPROM167US 5,754,475 AAdvanced Micro Devices, Inc. · 1998
- Programming of multi-level memory cells on a continuous word line142US 7,139,192 B1Samsung Electronics Co., Ltd. · 2006