Skip program verify for dynamic start voltage sampling
AssigneeIntel NDTM US LLC
InventorsArchana Tankasala, Sagar Upadhyay, Shantanu R. Rajwade, Aliasgar S. Madraswala
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AssigneeIntel NDTM US LLC
InventorsArchana Tankasala, Sagar Upadhyay, Shantanu R. Rajwade, Aliasgar S. Madraswala
Estimating the term…
Skip program verify for dynamic start voltage (DSV) sampling reduces latency of a program operation on multi-level cell (MLC) memory having at least two pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND device. The NAND device skips program verifies corresponding to higher levels of voltage thresholds during DSV sampling. As a result, the NAND device can reduce a total program time (tPROG) to program the MLC memory, and determine the dynamic start program voltage more quickly. The NAND device can improve an effective TLC NAND tPROG by as much as 2% without impacting the placement of the first sub-block being programmed. The skipped program verifies corresponding to the higher levels of voltage thresholds are resumed as soon as DSV sampling is complete.
A memory device comprising:
A multi-level cell (MLC) memory comprising:
A system comprising:
One or more non-transitory machine-readable media comprising a plurality of instructions encoded thereon that, in response to being executed, cause any of a device, system and apparatus having a memory in which to store data, to:
Dependencies are inferred from the claim text.