Dynamic program caching

A multi-level cell (MLC) memory comprising:

• at least three pages of memory in a memory array;
• and
• circuitry to program the at least three pages of memory at multiple threshold voltage levels in accordance with a dynamic program cache mode that is any one of enabled and disabled, including to:
• determine that a dynamic program cache mode of operation is enabled,
• execute a data I/O (input/output) operation to load a first page of the at least three pages, the first page determined as having data to program at a threshold voltage level of the multiple threshold voltage levels,
• execute one or more portions of a program operation in parallel, at least in part, with one or more data I/O operations to load remaining pages of the at least three pages, the remaining pages determined as having no data to program at the threshold voltage level, and
• wherein to execute the one or more portions of the program operation in parallel with the one or more data I/O operations to load the remaining pages reduces a latency of the program operation.

An apparatus comprising:

• a dynamic program cache mode that is any one of active and inactive;
• circuitry coupled to a multi-level cell (MLC) memory having at least three pages, the circuitry to reduce a latency of a program operation responsive to a determination that the dynamic program cache mode is active, the program operation to program one or more pages of the at least three pages at multiple threshold voltage levels, including to, for each threshold voltage level of the multiple threshold voltage levels:
• determine a presence of page data in a first page to program in the MLC memory,
• determine an absence of page data in one or more remaining pages to program in the MLC memory,
• issue a data I/O (input/output) operation to load the first page to the MLC memory, the first page having data to program at a threshold voltage level of the multiple threshold voltage levels, and
• issue one or more portions of the program operation to execute, at least in part, concurrently with one or more data I/O operations issued to load one or more remaining pages to the MLC memory, the one or more remaining pages having no data to program at the threshold voltage level.

A system comprising:

• a processor to any of enable and disable a dynamic program cache mode of a NAND device;
• a memory controller coupled to the NAND device, the memory controller to monitor the dynamic program cache mode;
• and
• a controller coupled to the NAND device, the controller to reduce a latency of a program operation to program at least three pages to the NAND device at a threshold voltage level of multiple threshold voltage levels, if the dynamic program cache mode is enabled, including to, for each threshold voltage level:
• determine a presence of page data in a first page at the threshold voltage level,
• determine an absence of page data in a next page at the threshold voltage level,
• issue a data I/O (input/output) operation to load the first page determined as having data to program at the threshold voltage level of the multiple threshold voltage levels at which the at least three pages are programmed to the NAND device, and
• issue one or more portions of the program operation to execute, at least in part, concurrently with data I/O (input/output) operations issued to load one or more next pages determined as having no data to program at the threshold voltage level.