Nonvolatile memory device including selection transistors and operating method thereof

A non-volatile memory device comprising:

• a plurality of cell strings each including a corresponding one of a plurality of source selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines;
• a peripheral circuit including a plurality of page buffers coupled to the cell strings through the respective bit lines, the peripheral circuit being coupled to the source selection transistors through a plurality of source selection lines and coupled to the memory cells through a plurality of word lines;
• and
• a control logic configured to control the peripheral circuit to:
• simultaneously perform a program operation on the source selection transistors,
• sequentially perform verification operations on respective groups of the source selection transistors, the groups being coupled to the respective source selection lines, and
• sequentially store results of the verification operations into respective data latch circuits within each of the page buffers.

A non-volatile memory device comprising:

• cell strings coupled between a bit line and a common source line, each of the cell strings including a selection transistor and memory cells serially coupled to each other, and the selection transistors of the cell strings being classified into groups coupled to respective selection lines;
• and
• a control circuit configured to:
• perform a program operation simultaneously on the selection transistors,
• perform verification operations on the respective groups to latch results of the respective verification operations, and
• adjust an operational voltage for a group, for which the latched result represents a fail, to a level lower than the operational voltage for a group, for which the latched result represents a pass, among the groups.