G11C 2211/4013
Memory devices with multiple cells per bit
Official title: Memory devices with multiple cells per bit, e.g. twin-cells
G11C2211/4013 (Memory devices with multiple cells per bit) appears on 146 US grants and 136 published applications in this corpus.
Search patents in G11C- Granted patents
- 146
- Published applications
- 136
- Assignees
- 51
- Inventors
- 164
- Latest grant
- 4 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1996 | 1 | 0 |
| 1997 | 0 | 0 |
| 1998 | 2 | 0 |
| 1999 | 2 | 0 |
| 2000 | 4 | 0 |
| 2001 | 1 | 2 |
| 2002 | 4 | 4 |
| 2003 | 3 | 9 |
| 2004 | 7 | 4 |
| 2005 | 9 | 9 |
| 2006 | 6 | 11 |
| 2007 | 8 | 4 |
| 2008 | 7 | 7 |
| 2009 | 4 | 2 |
| 2010 | 4 | 3 |
| 2011 | 2 | 3 |
| 2012 | 4 | 4 |
| 2013 | 2 | 3 |
| 2014 | 3 | 1 |
| 2015 | 1 | 2 |
| 2016 | 3 | 3 |
| 2017 | 4 | 10 |
| 2018 | 13 | 11 |
| 2019 | 13 | 12 |
| 2020 | 10 | 6 |
| 2021 | 6 | 5 |
| 2022 | 2 | 7 |
| 2023 | 10 | 6 |
| 2024 | 8 | 6 |
| 2025 | 2 | 2 |
| 2026 | 1 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages4 Aug 2026US 12,700,448 B2Micron Technology, Inc.
- Bank selection for refreshing27 May 2025US 12,315,548 B2Micron Technology, Inc.
- Ternary content addressable memory and decision generation method for the same28 Jan 2025US 12,211,550 B2Macronix International Co., Ltd.
- Setting levels for a programming operation in a neural network array24 Dec 2024US 12,176,039 B2Silicon Storage Technology, Inc.
- Apparatuses and methods for operations in a self-refresh state10 Dec 2024US 12,165,691 B2
- Ternary content addressable memory and decision generation method for the same24 Apr 2025US 2025/0131960 A1Macronix International Co., Ltd.
- Apparatuses and methods for operations in a self-refresh state20 Mar 2025US 2025/0095708 A1Lodestar Licensing Group LLC
- Content Addressable Memory Device Having Electrically Floating Body Transistor28 Nov 2024US 2024/0395323 A1Zeno Semiconductor, Inc.
- Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages10 Oct 2024US 2024/0339149 A1Micron Technology, Inc.
- Ternary content addressable memory and decision generation method for the same16 May 2024US 2024/0161826 A1Macronix International Co., Ltd.
Most cited
By later US patents
- Sense amplifier circuitry and architecture to write data into and/or read from memory cells263US 7,486,563 B2Innovative Silicon ISi SA · 2009
- Semiconductor memory cell, array, architecture and device, and method of operating same211US 7,085,153 B2Innovative Silicon S.A. · 2006
- Sense amplifier circuitry and architecture to write data into and/or read from memory cells151US 7,301,838 B2Innovative Silicon S.A. · 2007
- Shared sense amplifier for ferro-electric memory cell124US 6,574,135 B1Texas Instruments Incorporated · 2003
- Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval101US 6,449,204 B1Mitsubishi Denki Kabushiki Kaisha · 2002