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US 12,315,548 B2Granted
Bank selection for refreshing
AssigneeMicron Technology, Inc.
InventorsYang Lu, Kang-Yong Kim
Life of this patent
Estimating the term…
Abstract
In various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. Refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.
Claims17
An apparatus, comprising:
- mode registers;
- a plurality of banks of a memory device;
- and
- refresh bank circuitry coupled to the plurality of banks and the mode registers and configured to:
- receive a refresh command, wherein the refresh command comprises selector bits;
- receive mode register bits from the mode registers;
- and
- refresh a number of banks from the plurality of banks utilizing the mode register bits and the selector bits, wherein a first number of banks from the plurality of banks are refreshed utilizing a first value of the mode register bits, a first value of the selector bits and a portion of a plurality of address bits, wherein the first value of the mode register bits identifies a first bit of the plurality of address bits to not utilize.
5 more elements
A method, comprising:
- receiving a refresh command comprising a plurality of selector bits and address bits at refresh bank circuitry of a memory sub-system, wherein the refresh command comprises a plurality of selector bits, wherein the address bits comprise four or more address bits;
- determining a number of banks to refresh based on the plurality of selector bits and the address bits corresponding to the number of banks wherein refreshing the number of banks further comprises refreshing a single bank;
- and
- responsive to determining to refresh the number of banks using the selector bits, refreshing the number of banks.
1 more element
An apparatus, comprising:
- mode registers;
- a plurality of banks of a memory device;
- refresh bank circuitry coupled to the plurality of banks and the mode registers and configured to:
- receive a refresh command, wherein the refresh command comprises selector bits;
- receive mode register bits from the mode registers;
- and
- refresh a number of banks from the plurality of banks utilizing the mode register bits and the selector bits wherein a particular value of the selector bits is used to reference the mode register bits, wherein a number of banks from the plurality of banks are refreshed utilizing a first value of the mode register bits, a first value of the selector bits, and a portion of a plurality of address bits, wherein the first value of the mode register bits identifies a first bit of the plurality of address bits to not utilize.
4 more elements
Dependencies are inferred from the claim text.