Shared sense amplifier for ferro-electric memory cell

A ferro-electric memory device, comprising:

• an array of FeRAM memory cells associated with a pair of bitlines and a sense amplifier, wherein the array is further subdivided into segments which are individually selectable, and wherein each segment of the array is associated with the pair of bitlines, and wherein each segment comprises a plurality of FeRAM memory cells which are selectable and operable to store binary data in a ferro-electric capacitor;
• a segment decode logic operable to select a segment of an array associated with an FeRAM cell to be accessed for memory operations;
• a bitline decode logic operable to select a bitline segment associated with the sense amplifier and the FeRAM cell to be accessed;
• a bitline precharge circuit operable to precharge an initial voltage on the bitline segment associated with the sense amplifier and the FeRAM cell to be accessed;
• a plate line decode logic operable to select a plate line associated with the FeRAM cell to be accessed;
• a dummy cell precharge circuit operable to produce a precharge bias on a pair of dummy cells;
• the pair of dummy cells operable to generate a reference voltage which is a function of the precharge bias, and further operable to apply the reference voltage to the selected bitline segment associated with the FeRAM cell to be accessed for memory operations;
• and
• the sense amplifier associated with the FeRAM cell to be accessed and the selected bitline segment, operable to receive the reference voltage on one bitline of the selected bitline segment and a cell sense voltage on the other bitline of the selected bitline segment associated with the FeRAM cell to be accessed and operable to determine the logic state of the selected memory cell during a read operation.

A method of sensing a target memory cell in a read operation of an array of FeRAM 1T1C memory cells using a shared sense amplifier, comprising:

• selecting and precharging to about VCC/2, a common node of a set of segments of an array which is local to a segment containing the target memory cell;
• selecting and precharging to about Gnd, a bitline segment associated with a sense amp and the array containing the target memory cell;
• selecting the segment containing the target memory cell, by applying a voltage to the gate of a segment select transistor, thereby coupling the common node of the segment containing the target memory cell to the associated bitline segment;
• deselecting the precharge lines from the bitline segment and the common node of the segment containing the target memory cell;
• accessing the target memory cell by applying a voltage of about VCC to a word line and a plate line of the target memory cell;
• generating with a reference circuit, a reference voltage which is an averaged function of a biased FeRAM dummy cell applied to the bitline segment associated with the sense amplifier and the target memory cell;
• selecting the sense amplifier associated with the target memory cell;
• coupling the bitline segment shared by the sense amplifier to a data buffer to prepare for a data read from outside of the array, and for a restore operation;
• sensing and comparing with the sense amplifier a sense signal present at the common node, to the reference voltage generated by the dummy cells, after the sense signal has stabilized;
• storing the results of the comparison of the sense signal with the reference voltage temporarily in the data buffer;
• determining a “0” state or a “1” state of the target memory cell based on the comparison;
• writing and restoring the data in the data buffer to the target memory cell;
• and
• deselecting the plate line and the word line of the target memory cell, the sense amplifier, the data buffer, the bitline segment, and the segment of the array associated with the target memory cell, thereby yielding an accurate sensing of an FeRAM 1T1C cell in a read operation.

A method of performing a write operation to a target memory cell of an array of FeRAM 1T1C memory cells using a shared sense amplifier, comprising:

• selecting and precharging to about VCC/2, a common node of a set of segments of an array which are local to the segment containing the target memory cell;
• accessing the target memory cell by applying a voltage of about VCC to a word line and a plate line of the target memory cell;
• selecting the segment containing the target memory cell, by applying a voltage to the gate of a segment select transistor, thereby coupling the common node of the segment containing the target memory cell to the associated bitline segment;
• deselecting the precharge lines from the common node of the segment containing the target memory cell;
• coupling the bitline segment shared by the sense amplifier to a data buffer to prepare for a data write from outside of the array;
• storing the data to write temporarily in the data buffer;
• writing the data in the data buffer to the target memory cell;
• and
• deselecting the plate line and the word line of the target memory cell, the data buffer, the bitline segment, and the segment of the array associated with the target memory cell, thereby performing a write operation to a target memory cell of an array of FeRAM 1T1C memory cells.

A method of sensing a target memory cell in a read operation of an array of FeRAM 1C memory cells using a shared sense amplifier, comprising:

• selecting and precharging to about VCC/2, a common node of all segments of an array which is local to a segment containing the target memory cell, by applying a voltage to the gate of a segment select transistor in each segment, thereby coupling the common node of the segment containing the target memory cell to the associated bitline segment;
• selecting and precharging to about Gnd, a bitline segment associated with a sense amp and the array containing the target memory cell;
• selecting and precharging to about Gnd, a plate line associated with the target memory cell;
• selecting and precharging to about VCC/2, all other plate lines of the array which are not associated with the target memory cell;
• deselecting the segments of the array which are not associated with the target memory cell;
• accessing the target memory cell by applying a voltage of about VCC to a plate line of the target memory cell;
• generating with a reference circuit, a reference voltage which is an averaged function of a biased FeRAM dummy cell applied to the bitline segment associated with the sense amplifier and the target memory cell;
• selecting the sense amplifier associated with the target memory cell;
• coupling the bitline segment shared by the sense amplifier to a data buffer to prepare for a data read from outside of the array, and for a restore operation;
• sensing and comparing with the sense amplifier a sense signal present at the common node, to the reference voltage generated by the dummy cells, after the sense signal has stabilized;
• storing the results of the comparison of the sense signal with the reference voltage temporarily in the data buffer;
• determining a “0” state or a “1” state of the target memory cell based on the comparison;
• writing and restoring the data in the data buffer to the target memory cell;
• and
• deselecting the plate line of the target memory cell, the sense amplifier, the data buffer, the bitline segment, and the segments of the array which are local to the target memory cell, thereby yielding an accurate sensing of an FeRAM 1C cell in a read operation.

A method of performing a write operation to a target memory cell of an array of FeRAM 1C memory cells using a shared sense amplifier, comprising:

• selecting all segments of an array which is local to a segment containing the target memory cell, by applying a voltage to the gate of a segment select transistor in each segment, thereby coupling a common node of the segment containing the target memory cell to the associated bitline segment;
• selecting and precharging to about Gnd, a bitline segment associated with a sense amp and the array containing the target memory cell;
• selecting and precharging to about Gnd, a plate line associated with the target memory cell;
• selecting and precharging to about VCC/2, all other plate lines of the array which are not associated with the target memory cell;
• deselecting the segments of the array which are not associated with the target memory cell;
• accessing the target memory cell by applying a voltage of about VCC to a plate line of the target memory cell;
• deselecting the bitline segment associated with a sense amp and the array containing the target memory cell, which was precharging to about Gnd;
• coupling the bitline segment shared by the sense amplifier to a data buffer to prepare for a data write from outside of the array;
• storing the data to write temporarily in the data buffer;
• writing the data in the data buffer to the target memory cell;
• and
• deselecting the plate line of the target memory cell, the data buffer, the bitline segment, and the segment of the array associated with the target memory cell, thereby performing a write operation to a target memory cell of an array of FeRAM 1C memory cells.