US 7,085,153 B2 · Semiconductor memory cell, array, architecture and device, and method of operating same

Abstract

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

Claims41

Dependent claims

A semiconductor dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising:

first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
wherein the memory cell is in:
(1) the first data state when the first transistor is in the first state and the second transistor is in the second state, and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state;
and
wherein the memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include different voltage amplitudes, and
the second and fourth control signals include substantially the same voltage amplitudes.

10 more elements

A semiconductor memory array, comprising:

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes:
first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating:
and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
wherein each memory cell is in:
(1) the first data state when its first transistor is in the first state and its second transistor is in the second state, and (2) the second data state when its first transistor is in the second state and its second transistor is in the first state;
and
wherein each memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include different voltage amplitudes, and
the second and fourth control signals include substantially the same voltage amplitudes.

11 more elements

A semiconductor dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising:

first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
wherein the memory cell is in:
(1) the first data state when the first transistor is in the first state and the second transistor is in the second state, and (2) the second data state when the first transistor is in the second state and the second transistor is in the first state;
and
wherein the memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include substantially the same voltage amplitudes, and
the second and fourth control signals include different voltage amplitudes.

10 more elements

A semiconductor memory array, comprising:

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes:
first and second transistors, wherein each transistor includes:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
and
a gate spaced apart from, and capacitively coupled to, the body region;
wherein each transistor includes (i) a first state representative of a first charge in the body region, and (ii) a second state representative of a second charge in the body region;
and
wherein each memory cell is in:
(1) the first data state when its first transistor is in the first state and its second transistor is in the second state, and (2) the second data state when its first transistor is in the second state and its second transistor is in the first state;
and
wherein each memory cell is programmed to a first data state by applying (i) a first control signal to the gate of the first transistor and a second control signal to the drain of the first transistor and (ii) a third control signal to the gate of the second transistor and a fourth control signal to the drain of the second transistor wherein:
the first and third control signals include substantially the same voltage amplitudes, and
the second and fourth control signals include different voltage amplitudes.

12 more elements

Dependencies are inferred from the claim text.

Semiconductor memory cell, array, architecture and device, and method of operating same

Life of this patent

Semiconductor memory cell, array, architecture and device, and method of operating same

Life of this patent

Abstract

Claims41