G06F 9/3842
Speculative instruction execution
Official title: {Speculative instruction execution}
G06F9/3842 (Speculative instruction execution) appears on 2,870 US grants and 2,438 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,870
- Published applications
- 2,438
- Assignees
- 365
- Inventors
- 3,426
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 3 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 1 | 0 |
| 1986 | 3 | 0 |
| 1987 | 3 | 0 |
| 1988 | 9 | 0 |
| 1989 | 8 | 0 |
| 1990 | 9 | 0 |
| 1991 | 6 | 0 |
| 1992 | 12 | 0 |
| 1993 | 14 | 0 |
| 1994 | 21 | 0 |
| 1995 | 34 | 0 |
| 1996 | 40 | 0 |
| 1997 | 65 | 0 |
| 1998 | 115 | 0 |
| 1999 | 106 | 0 |
| 2000 | 88 | 0 |
| 2001 | 86 | 26 |
| 2002 | 74 | 76 |
| 2003 | 95 | 89 |
| 2004 | 92 | 133 |
| 2005 | 84 | 125 |
| 2006 | 86 | 104 |
| 2007 | 84 | 82 |
| 2008 | 97 | 129 |
| 2009 | 87 | 104 |
| 2010 | 104 | 89 |
| 2011 | 85 | 72 |
| 2012 | 59 | 65 |
| 2013 | 60 | 80 |
| 2014 | 66 | 107 |
| 2015 | 76 | 88 |
| 2016 | 123 | 90 |
| 2017 | 91 | 122 |
| 2018 | 96 | 99 |
| 2019 | 111 | 114 |
| 2020 | 118 | 130 |
| 2021 | 141 | 108 |
| 2022 | 109 | 94 |
| 2023 | 91 | 102 |
| 2024 | 92 | 56 |
| 2025 | 77 | 77 |
| 2026 | 42 | 77 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Branch target buffer run-ahead8 Sep 2026US 12,730,646 B2Microsoft Technology Licensing, LLC
- Systems and methods for parallel data processing1 Sep 2026US 12,724,612 B2Samsung Electronics Co., Ltd.
- Automatic hardware speculation suppression1 Sep 2026US 12,724,613 B2Advanced Micro Devices, Inc.
- Lightweight out of order scheduler for processing units25 Aug 2026US 12,717,584 B2The Trustees of Princeton University
- Speculative execution using a page-level tracked load order queue11 Aug 2026US 12,705,054 B2Advanced Micro Devices, Inc.
- Phase-Aware Resource Tuning Using Behavioral Inference8 Oct 2026US 2026/0310503 A1Arm Limited
- Branch target buffer run-ahead1 Oct 2026US 2026/0299957 A1Microsoft Technology Licensing, LLC
- Prediction entry allocation24 Sep 2026US 2026/0288461 A1Arm Limited
- Branch target buffer victim cache3 Sep 2026US 2026/0259735 A1Microsoft Technology Licensing, LLC
- Speculative Decoding Systems and Methods Having Improved Throughput3 Sep 2026US 2026/0259737 A1
Most cited
By later US patents
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture418US 8,555,037 B2Apple Inc. · 2013
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode317US 5,239,654 ATexas Instruments Incorporated · 1993