Speculative execution using a page-level tracked load order queue
AssigneeAdvanced Micro Devices, Inc.
InventorKrishnan V. Ramani
Life of this patent
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Abstract
Speculative execution using a page-level tracked load order queue includes: determining that a first load instruction targets a determined memory region; and in response to the first load instruction targeting the determined memory region, adding an entry to a page-level tracked load order queue instead of a load order queue, where the entry indicates a page address of a target of the first load instruction.
Claims20
A method for speculative execution using multiple queues including at least a first queue and a second queue, the method comprising:
- adding a first entry to the first queue for a first load instruction based on the first load instruction targeting a memory area outside of a current program stack, wherein each entry in the first queue identifies a particular memory address;
- and
- adding a second entry to the second queue for a second load instruction based on the second load instruction targeting the current program stack, wherein each entry in the second queue identifies a page of memory.
A load store unit for speculative execution using multiple queues including at least a first queue and a second queue, the load store unit configured to:
- add a first entry to the first queue for a first load instruction based on the first load instruction targeting a memory area outside of a current program stack, wherein each entry in the first queue identifies a particular memory address;
- and
- add a second entry to the second queue in response to a second load instruction that targets the current program stack, wherein each entry in the second queue identifies a page of memory.
A processor for speculative execution using multiple queues, comprising:
- a first queue comprising a plurality of entries each identifying a particular memory address, wherein the processor is configured to add a first entry to the first queue for a first load instruction based on the first load instruction targeting a memory area outside of a current program stack;
- and
- a second queue comprising a plurality of entries each identifying a page of memory, wherein the processor is configured to add a second entry to the second queue for a second load instruction based on the second load instruction targeting the current program stack.
Dependencies are inferred from the claim text.