Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode

A multi-processor system having a single instruction multiple data (SIMD) mode and a multiple instruction multiple data (MIMD) mode, said multi-processor system comprising:

• a plurality of processors, each processors having a data port and an instruction memory port and operating from instructions provided to said instruction port;
• a plurality of memories including at least one data memory corresponding to each of said processors and an instruction memory corresponding to each of said processors;
• a switch matrix connected to each of said plurality of processors and each of said plurality of memories, said switch matrix
• when operating in the multiple instruction multiple data (MIMD) mode said switch matrix:
• (1) connecting between said instruction port of each processor and said corresponding instruction memory for supplying corresponding instructions to each of said processors, (2) connecting between said data port of each of said processors and each of said plurality of memories except said instruction memories, and (3) prohibiting connection between said data port of each of said processors and said instruction memories, and
• when operating in the single instruction multiple data (SIMD) mode said switch matrix:
• (1) permitting connecting between said instruction port of a first processor of said plurality of processors and said corresponding instruction memory for supplying a single instruction to all of said processors, (2) connecting between said data port of each of said plurality of processors and each of said plurality of memories including said instruction memories corresponding to processors other than said first processor, and (3) prohibiting connection between said data port of each of said processors and said instruction memory corresponding to said first processor.

A multi-processor system operable in either a single instruction multiple data (SIMD) mode or in a multiple system comprising:

• a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode for each of said plurality of processors;
• a plurality of processors, each processors having a data port and an instruction portion and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;
• a plurality of memories, said plurality of memories including at least one data memory corresponding to each of said processors and an instruction memory corresponding to each of said processors;
• a switch matrix connected to said SIMD/MIMD mode register, to each of said plurality of processors and each of said plurality of memories, said switch matrix including
• a set of first links, each first link connected to a corresponding memory,
• a set of second links, each second line connected to said data ports of a corresponding processor,
• a third link having a plurality of sections equal in number to the number of said processors, each section connected to said instruction port of a corresponding one of said processors,
• a plurality of buffers disposed between adjacent sections of said third link forming a serial chain from a first processor to a last processor, each buffer connecting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode for a corresponding processor, and isolating said adjacent sections of said third link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode for the corresponding processor, and
• a plurality of crosspoints disposed at intersections between said first links and said second links at intersections between said first links and said sections of said third link, said plurality of crosspoints including (1) a first crosspoint disposed at the intersection of said section of said third link connected to said instruction port of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to provide connection, (2) a set of second crosspoints disposed at the intersection of said section of said third link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode for said processor corresponding to said instruction memory and enabled to provide connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode for said processor corresponding to said instruction memory, (3) a set of third crosspoints disposed at the intersection of said first links connected to said instruction memories and said second links connected to said data ports of said plurality of processors, said set of third crosspoints disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode for said processor corresponding to said instruction memory and enabled to provide connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode for said processor corresponding to said instruction memory;
• whereby said instruction port of each processor is connected to said instruction memory corresponding to the first processor in a serial chain in the single instruction multiple data (SIMD) mode, said instruction port of each processor in the multiple instruction multiple data (MIMD) mode is connected to said corresponding instruction memory, and access to said instruction memories via said data ports of said plurality of processors is prohibited when the corresponding processor is in the single instruction multiple data (SIMD) mode and permitted when the corresponding processor is in the multiple instruction multiple data (MIMD) mode.

A computer implemented method of operating a plurality of processors in either a single instruction multiple data (SIMD) mode or in a multiple instruction multiple data (MIMD) mode in conjunction with a plurality of memories supplying data and instructions to the processors, the method comprising the computer implemented steps of:

• storing an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode for each processor;
• connecting through a switch matrix a first processor in a serial chain of processors operating in the single instruction multiple data (SIMD) mode to a corresponding instruction memory;
• connecting through said switch matrix each processor in the serial chain of processors operating in the single instruction multiple data (SIMD) mode other than the first processor in the serial chain of processors operating in the single instruction multiple data (SIMD) mode to said instruction memory corresponding to the first processor in the serial chain of processors operating in the single instruction multiple data (SIMD) mode;
• connecting each processor in the multiple instruction multiple data (MIMD) mode to a corresponding instruction memory so that each processor has its own corresponding construction memory;
• prohibiting any other processor from accessing the instruction memory corresponding to a processor in the multiple instruction multiple data (MIMD) mode;
• and
• providing access through said switch matrix to any other processor to the instruction any other processor to the instruction memories corresponding to the other processor other than the first processor in a serial chain of processors operating in the single instruction multiple data (SIMD) mode.