G06F 9/3836
Instruction issuing
Official title: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
G06F9/3836 (Instruction issuing) appears on 10,000 US grants and 9,311 published applications in this corpus.
Search patents in G06F- Granted patents
- 10,000
- Published applications
- 9,311
- Assignees
- 1,120
- Inventors
- 11,072
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 3 | 0 |
| 1978 | 2 | 0 |
| 1979 | 0 | 0 |
| 1980 | 3 | 0 |
| 1981 | 5 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 6 | 0 |
| 1985 | 2 | 0 |
| 1986 | 8 | 0 |
| 1987 | 4 | 0 |
| 1988 | 15 | 0 |
| 1989 | 17 | 0 |
| 1990 | 22 | 0 |
| 1991 | 22 | 0 |
| 1992 | 33 | 0 |
| 1993 | 42 | 0 |
| 1994 | 60 | 0 |
| 1995 | 84 | 0 |
| 1996 | 112 | 0 |
| 1997 | 146 | 0 |
| 1998 | 308 | 0 |
| 1999 | 275 | 0 |
| 2000 | 229 | 0 |
| 2001 | 243 | 53 |
| 2002 | 204 | 224 |
| 2003 | 227 | 279 |
| 2004 | 211 | 378 |
| 2005 | 223 | 330 |
| 2006 | 251 | 326 |
| 2007 | 247 | 294 |
| 2008 | 303 | 420 |
| 2009 | 255 | 330 |
| 2010 | 330 | 270 |
| 2011 | 313 | 246 |
| 2012 | 251 | 261 |
| 2013 | 245 | 292 |
| 2014 | 258 | 383 |
| 2015 | 268 | 362 |
| 2016 | 435 | 414 |
| 2017 | 401 | 462 |
| 2018 | 389 | 366 |
| 2019 | 445 | 479 |
| 2020 | 446 | 604 |
| 2021 | 562 | 549 |
| 2022 | 520 | 515 |
| 2023 | 527 | 471 |
| 2024 | 443 | 378 |
| 2025 | 382 | 339 |
| 2026 | 216 | 286 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Arithmetic processing apparatus which executes plurality of instructions in parallel and sequentially from executable instructions and method for arithmetic processing29 Sep 2026US 12,748,598 B2Fujitsu Limited
- Application programming interface to indicate a number of registers to be used by instructions29 Sep 2026US 12,748,599 B1NVIDIA Corporation
- Systems, methods, and apparatuses for heterogeneous computing29 Sep 2026US 12,748,618 B2Intel Corporation
- Data processing apparatus and method for providing compiler with polyhedral scheduler29 Sep 2026US 12,748,623 B2Huawei Technologies Co., Ltd.
- Distributed control plane for reformatting communication between a container orchestration platform and a distributed storage architecture22 Sep 2026US 12,743,319 B2NetApp, Inc.
- Phase-Aware Resource Tuning Using Behavioral Inference8 Oct 2026US 2026/0310503 A1Arm Limited
- Efficient matrix multiply and add with a group of warps1 Oct 2026US 2026/0299943 A1NVIDIA Corporation
- Branch target buffer run-ahead1 Oct 2026US 2026/0299957 A1Microsoft Technology Licensing, LLC
- Memory dependence prediction1 Oct 2026US 2026/0299958 A1Advanced Micro Devices, Inc.
- Tamper-Resistant Code Obfuscation with Control Flow Breaking1 Oct 2026US 2026/0300450 A1Zimperium, Inc.
Most cited
By later US patents
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Vector processor system420US 8,356,144 B22013
- Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture418US 8,555,037 B2Apple Inc. · 2013
- Processing architecture having a compare capability417US 7,028,170 B2Sun Microsystems, Inc. · 2006