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US 12,724,613 B2Granted
Automatic hardware speculation suppression
AssigneeAdvanced Micro Devices, Inc.
InventorsDaniel Simon McFarlin, John Kalamatianos
Life of this patent
Estimating the term…
Abstract
In some implementations, the device may include detecting a speculative load hardening indicator in a first block of code. In addition, the device may include selectively suppressing hardware speculative execution for instructions in the first block of code associated with the detected speculative load hardening indicator.
Claims18
A method comprising:
- detecting, by a processor, a conditional branch instruction within a first block of code of a software program;
- checking, by the processor, a next flag-consuming instruction following the conditional branch instruction to detect whether a conditional move instruction or fence instruction indicating speculative load hardening is present in the first block of code;
- and
- in response to detecting the conditional move instruction or fence instruction indicating speculative load hardening within the first block of code, selectively suppressing, by the processor, hardware speculative execution for instructions in the first block of code;
- evaluating, by the processor, instructions within a second block of code to detect that the second block of code does not include a conditional move instruction or fence instruction indicating speculative load hardening;
- and
- in response to determining that the second block of code does not include the conditional move instruction or fence instruction indicating speculative load hardening, not suppressing hardware speculative execution for the second block of code.
4 more elements
A device comprising:
- a fetch circuit configured to fetch instructions from a plurality of blocks of code;
- a decode circuit configured to:
- detect a conditional branch instruction within a first block of code of the plurality of blocks of code;
- record a predicted branch condition for the conditional branch instruction;
- check a next flag-consuming instruction following the conditional branch instruction to detect whether a conditional move instruction or fence instruction indicating speculative load hardening is present in the first block of code;
- and
- in response to detecting the conditional move instruction or fence instruction indicating speculative load hardening within the first block of code, selectively suppress hardware speculative execution for instructions in the first block of code, wherein the predicted branch condition is not loaded for concurrent execution of subsequent instructions;
- evaluate instructions within a second block of code of the plurality of blocks of code to detect that the second block of code does not include a conditional move instruction or fence instruction indicating speculative load hardening;
- and
- in response to determining that the second block of code does not include the conditional move instruction or fence instruction indicating speculative load hardening, not suppress hardware speculative execution for the second block of code;
- and
- an execution circuit configured to execute the instructions from the plurality of blocks of code.
9 more elements
A non-transitory computer-readable storage medium storing instructions that, when executed by a computing system, cause the computing system to perform operations comprising:
- detecting a conditional branch instruction within a first block of code;
- recording a predicted branch condition for the conditional branch instruction;
- checking a next flag-consuming instruction following the conditional branch instruction to detect whether a conditional move instruction or fence instruction indicating speculative load hardening is present in the first block of code;
- and
- in response to detecting the conditional move instruction or fence instruction indicating speculative load hardening within the first block of code, selectively suppressing hardware speculative execution for instructions in the first block of code, wherein the predicted branch condition is not loaded for concurrent execution of subsequent instructions;
- evaluating instructions within a second block of code to detect that the second block of code does not include a conditional move instruction or fence instruction indicating speculative load hardening;
- and
- in response to determining that the second block of code does not include the conditional move instruction or fence instruction indicating speculative load hardening, not suppressing hardware speculative execution for the second block of code.
5 more elements
Dependencies are inferred from the claim text.