G06F 9/3009
Thread control instructions
Official title: {Thread control instructions}
G06F9/3009 (Thread control instructions) appears on 821 US grants and 976 published applications in this corpus.
Search patents in G06F- Granted patents
- 821
- Published applications
- 976
- Assignees
- 199
- Inventors
- 1,703
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 3 | 0 |
| 1997 | 0 | 0 |
| 1998 | 3 | 0 |
| 1999 | 3 | 0 |
| 2000 | 6 | 0 |
| 2001 | 6 | 0 |
| 2002 | 5 | 7 |
| 2003 | 7 | 12 |
| 2004 | 4 | 14 |
| 2005 | 6 | 22 |
| 2006 | 5 | 13 |
| 2007 | 6 | 17 |
| 2008 | 11 | 22 |
| 2009 | 19 | 11 |
| 2010 | 23 | 15 |
| 2011 | 10 | 18 |
| 2012 | 14 | 19 |
| 2013 | 19 | 26 |
| 2014 | 19 | 23 |
| 2015 | 26 | 34 |
| 2016 | 33 | 49 |
| 2017 | 41 | 74 |
| 2018 | 40 | 61 |
| 2019 | 63 | 82 |
| 2020 | 79 | 64 |
| 2021 | 78 | 96 |
| 2022 | 77 | 76 |
| 2023 | 72 | 75 |
| 2024 | 75 | 60 |
| 2025 | 37 | 39 |
| 2026 | 25 | 47 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Interrupt handling6 Oct 2026US 12,754,760 B2BlackBerry Limited
- Dynamic memory power capping with criticality awareness29 Sep 2026US 12,748,620 B2Advanced Micro Devices, Inc.
- Synchronous microthreading22 Sep 2026US 12,743,339 B2Intel Corporation
- Hierarchical thread scheduling based on multi-parameter signal barriers25 Aug 2026US 12,717,582 B2Intel Corporation
- Application programming interface to wait on matrix multiply-accumulate18 Aug 2026US 12,710,961 B2NVIDIA Corporation
- Efficient matrix multiply and add with a group of warps1 Oct 2026US 2026/0299943 A1NVIDIA Corporation
- Increasing reliability and performance of control plane traffic for optical lane multiplexing1 Oct 2026US 2026/0299993 A1Viavi Solutions Inc.
- Systems and methods of reducing an impact of false-positive detections in a kernel17 Sep 2026US 2026/0278098 A1Robert Bosch GmbH
- Method, apparatus, device, medium and product for processing stack information10 Sep 2026US 2026/0267648 A1
- Multi-threaded data dependencies10 Sep 2026US 2026/0267652 A1Arm Limited
Most cited
By later US patents
- Altering thread priorities in a multithreaded processor356US 6,212,544 B1International Business Machines Corporation · 2001
- Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths274US 6,272,616 B1Agere Systems Guardian Corp. · 2001
- Thread switch control in a multithreaded processor system236US 6,567,839 B1International Business Machines Corporation · 2003
- Method and system for executing a program within a multiscalar processor by processing linked thread descriptors177US 6,212,542 B1International Business Machines Corporation · 2001
- Executing speculative parallel instructions threads with forking and inter-thread communication168US 5,812,811 AInternational Business Machines Corporation · 1998