Thread switch control in a multithreaded processor system

A method of computer processing, comprising:

• (a) storing a first state of at least one active thread in at least one hardware register in hardware thread switch logic unit integrated with a multithread processor in a processor core;
• (b) storing a second state of at least one background thread in the at least one hardware register in the hardware thread switch logic unit;
• (c) executing the at least one active thread in a multithreaded processor;
• (d) changing the first state of the at least one active thread if any one of the following conditions occur:
• (i) execution of the at least one active thread stalls because of a latency event represented by entries in a register in the hardware thread switch logic unit;
• (ii) altering priority of the at least one active thread to be equal to or lower than priority of the at least one background thread;
• (e) determining in the hardware thread switch logic unit if changing the first state of the at least one active thread causes the multithreaded processor to switch execution to the at least one background thread by:
• (i) determining if the latency event is a thread switch event;
• and
• (ii) determining if the thread switch event is enabled in a register in the hardware thread switch logic unit;
• (f) switching execution to the at least one background thread under one of the following conditions:
• (i) counting the number of processor cycles that the at least one active thread has been executing and when the number of execution cycles is equal to a time-out value, then switching execution to the at least one background thread;
• (ii) receiving an external interrupt signal and then switching execution to the at least one background thread;
• (iii) at least one bit in a thread switch control register in the hardware thread switch logic unit corresponding to the thread switch event is enabled;
• (iv) changing priority of the at least one background thread to a priority equal to or higher than the priority of the at least one active thread;
• (g) not switching execution to the at least one background thread under one of the following conditions:
• (i) determining the latency event is not a thread switch event;
• (ii) determining that the thread switch event is not enabled in the hardware thread switch logic unit;
• (iii) counting in the hardware thread switch logic unit a number of thread switches that has occurred away from the at least one active thread, then comparing the number with a count threshold and signaling the thread switch control register when the number is equal to the count threshold.

A data processing system, comprising:

• (a) a central processing unit comprising a multithreaded processor capable of executing at least one active thread, a hardware thread switch logic unit having at least one register capable of storing the state of at least one active thread and at least one background thread, a plurality of execution units, a plurality of registers, a hardware storage control unit, and an instruction unit;
• wherein the execution units, the registers, the hardware thread switch logic unit, the hardware storage control unit, and the instruction unit are integrated with the multithreaded processor in the central processing unit;
• (b) a plurality of cache memories connected intermediate between said central processing unit and a main memory;
• (c) a plurality of external connections comprising a bus interface, a bus, at least one input/output processor connected to at least one of the following:
• a tape drive, a data storage device, a computer network, a fiber optics communication, a workstation, a peripheral device, an information network;
• any of which are capable of transmitting data and instructions to the central processing unit over the bus;
• wherein when the at least one active thread stalls execution, the event and reason thereof are communicated to the hardware storage control unit, the hardware storage control unit sends a corresponding signal to the hardware thread switch logic unit, and the hardware thread switch logic unit changes the state of the at least one active thread in said at least one register and determines if the multithreaded processor will switch threads and execute one of said at least one background thread.

A computer processing system comprising:

• (a) an integrated multithreaded processor in a central processing unit;
• (b) a thread switch logic unit having at least one hardware thread state register and a hardware thread switch control register in the central processing unit integrated with the multithreaded processor;
• and
• (c) a hardware storage control unit in the central processing unit integrated with the multithreaded processor and the thread switch logic unit
• wherein the hardware storage control unit receives data, instructions, and input for the multithreaded processor and signals the thread switch logic unit and the multithreaded processor according to the data, instructions, and input, and in response thereto the thread switch logic unit outputs signals to the multithreaded processor.

A computer processing system comprising:

• a central processing unit having a plurality of integrated circuits connected together configured as at least one multithreaded processor capable of executing at least one active thread and storing at least one background thread of a plurality of threads of instructions, at least one execution unit wherein the data and instructions are executed;
• a hardware storage control unit comprising a transition cache, at least a first multiplexer to transmit instructions from the transition cache or an instruction cache or a memory to an instruction unit, and at least a second multiplexer to transmit data from at least one data cache or the transition cache or a memory to the at least one execution unit, at least one sequencer unit to provide control signals to at least the memory, the caches, the multiplexers, and the execution units;
• a thread switch logic unit comprising a hardware thread state register to store states of the at least one active and background thread, and a hardware thread switch control register having bits to enable a plurality of thread switch events, the thread switch logic unit also receiving and transmitting control signals from and to the sequencer unit, and
• a plurality of cache memories including the at least one data cache and the instruction cache,
• wherein the thread switch logic unit receives signals from the hardware storage control unit characterizing the state of the plurality of threads in the multithreaded processor and in response thereto, determines whether to switch execution from the at least one active thread in the multithreaded processor.

A computer processor system, comprising:

• (a) means to process at least one active thread of instructions integrated in a hardware multithreaded central processing unit;
• (b) means to store a state of the at least one active thread in a hardware register integrated in the multithreaded central processing unit;
• (c) means to store a state of at least one background thread of instructions in a hardware register integrated in the multithreaded central processing unit;
• (d) means to change the states of the at least one active thread and the at least one background thread in the hardware registers,
• (e) means, responsive to the means to change the states, to switch threads so that the processing means processes the at least one background thread.

A computer processor, comprising:

• a multithreaded processor capable of executing at least one of a plurality of threads of instructions in a central processing unit;
• a first plurality of hardware registers integrated with the multithreaded processor in the central processing unit, the first plurality of hardware registers having a plurality of bits to indicate the states of each of the plurality of threads of instructions;
• a second plurality of hardware registers integrated with the multithreaded processor in the central processing unit, the second plurality of hardware registers having a plurality of bits to indicate a plurality of first events upon which the multithreaded processor will switch execution of threads;
• wherein the computer processing system can switch threads if a second event which changes the states of any of the plurality of threads of instructions in the first plurality of hardware registers is enabled in the second plurality of hardware registers.