Multi-threaded data dependencies

Abstract

A data processing apparatus includes multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Decoder circuitry responds to a first occurrence of a detach instruction to generate a first micro-thread in respect of a first block of instructions, and a second occurrence of the detach instruction to generate a second micro-thread in respect of a second block of instructions. The second block of instructions comprises a data dependency in respect of a resource accessed in the first block of instructions. Also provided is a data processing apparatus with input circuitry that receives input code with a first block of instructions and a second block of instructions. Output circuitry produces output code corresponding to the first block of instructions and the second block of instructions. Processing circuitry generates the output code based on the input code. The processing circuitry generates: a first hint instruction, within the output code corresponding to the first block of instructions, that indicates an availability of a resource, and a second hint instruction, within the output code corresponding to the second block of instructions, that indicates a requirement of the resource. The second block of instructions has a data dependency in respect of a resource accessed in the first block of instructions.

Dependencies are inferred from the claim text.