Hierarchical thread scheduling based on multi-parameter signal barriers

A graphics processing apparatus comprising:

• a memory device;
• and
• a graphics processing unit (GPU) coupled to the memory device, the GPU configured to:
• execute a first instruction thread;
• determine if a signal barrier is associated with the first instruction thread, wherein the signal barrier includes a signal barrier identifier, wherein the signal barrier identifier is one of a plurality of values;
• for the signal barrier associated with the first instruction thread, determine if the signal barrier is cleared;
• and
• based on the signal barrier being cleared, permit a waiting instruction thread associated with the signal barrier identifier to commence with execution but not permit a second waiting instruction thread that is not associated with the signal barrier identifier to commence with execution, wherein the signal barrier comprises a single command that specifies multiple parameters and wherein the multiple parameters specify:
• a number of producer threads subject to the signal barrier, a number of consumer threads subject to the signal barrier, whether the signal barrier applies to consumer type threads, whether the signal barrier applies to producer type threads, a memory sharing scheme, and an instruction pointer to an instruction queue.