G06F 9/30079
Pipeline control instructions
Official title: {Pipeline control instructions, e.g. multicycle NOP}
G06F9/30079 (Pipeline control instructions) appears on 414 US grants and 410 published applications in this corpus.
Search patents in G06F- Granted patents
- 414
- Published applications
- 410
- Assignees
- 146
- Inventors
- 815
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 3 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 8 | 0 |
| 1997 | 9 | 0 |
| 1998 | 11 | 0 |
| 1999 | 5 | 0 |
| 2000 | 3 | 0 |
| 2001 | 7 | 0 |
| 2002 | 3 | 5 |
| 2003 | 1 | 5 |
| 2004 | 5 | 3 |
| 2005 | 3 | 4 |
| 2006 | 4 | 9 |
| 2007 | 6 | 6 |
| 2008 | 5 | 7 |
| 2009 | 6 | 7 |
| 2010 | 6 | 3 |
| 2011 | 3 | 15 |
| 2012 | 3 | 7 |
| 2013 | 15 | 8 |
| 2014 | 12 | 21 |
| 2015 | 6 | 23 |
| 2016 | 23 | 16 |
| 2017 | 19 | 17 |
| 2018 | 17 | 17 |
| 2019 | 24 | 20 |
| 2020 | 21 | 29 |
| 2021 | 19 | 25 |
| 2022 | 34 | 53 |
| 2023 | 32 | 27 |
| 2024 | 45 | 30 |
| 2025 | 18 | 29 |
| 2026 | 28 | 24 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Dynamic reconfiguration of a unified core processor to a multi-core processor22 Sep 2026US 12,743,395 B2NVIDIA Corporation
- Backward compatibility testing of software in a mode that attempts to induce skew15 Sep 2026US 12,737,282 B2Sony Interactive Entertainment Inc.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Maintaining state information24 Sep 2026US 2026/0288467 A1Arm Limited
- Cache coherence shared state suppression24 Sep 2026US 2026/0288640 A1
- Merging data for write allocate10 Sep 2026US 2026/0267679 A1
- Pipeline arbitration3 Sep 2026US 2026/0259764 A1
- Memory controller management techniques30 Jul 2026US 2026/0220078 A1Intel Corporation
Most cited
By later US patents
- Processor-cache system and method417US 9,047,193 B2Shanghai Xin Hao Micro Electronics Co. Ltd. · 2015
- Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths274US 6,272,616 B1Agere Systems Guardian Corp. · 2001
- Adaptive power management processes, circuits and systems93US 5,754,436 ATexas Instruments Incorporated · 1998
- Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor92US 6,216,223 B1Billions of Operations Per Second, Inc. · 2001
- Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching83US 6,021,485 AInternational Business Machines Corporation · 2000