Dynamic reconfiguration of a unified core processor to a multi-core processor

A processor comprising a first core, the first core corresponding to a first pipeline and a first set of hardware structures, wherein the processor is to:

• execute a first thread on the first core;
• and
• in response to a command to operate the processor with a plurality of cores:
• partition the first core to obtain a second core and a third core, wherein the second core comprises a second pipeline and a second set of hardware structures, and the third core comprises a third pipeline and a third set of hardware structures;
• execute the first thread on the second pipeline of the second core;
• and
• execute a second thread on the third pipeline of the third core;
• save at least one of an architectural state or a microarchitectural state of the first core to a side structure of the processor;
• restore at least one of the architectural state or the microarchitectural state of the first core to the second core;
• and
• restore at least one of an architectural state or a microarchitectural state associated with the second thread to the third core.

A system comprising:

• a memory subsystem;
• and
• a processing device coupled to the memory subsystem, wherein the processing device is to:
• execute a first thread on a first pipeline of a first core of the processing device, the first core comprising a first set of hardware structures and the first pipeline comprising a set of sequential processing stages;
• and
• in response to a command to operate the processing device with a plurality of cores:
• partition the first core to obtain a second core and a third core, wherein to partition the first core, the processing device is to partition the first pipeline to obtain a second pipeline and a third pipeline such that each of the second pipeline and the third pipeline is an independent, statically partitioned pipeline of sequential processing stages without sharing pipeline stages with the other pipeline, and partition the first set of hardware structures to obtain a second set of hardware structures and a third set of hardware structures;
• execute the first thread on the second pipeline of the second core of the processing device, the second core comprising the second set of hardware structures;
• and
• execute a second thread on the third pipeline of the third core of the processing device, the third core comprising the third set of hardware structures.