Adaptive power management processes, circuits and systems

A process for power management of a computer system having a clock, comprising the steps of:

• sampling different system activity levels and producing system activity signals representative of the system activity levels;
• supplying weighted activity output signals adjustably weighting the system activity levels;
• and
• continually filtering the weighted activity output signals to produce a series of duty-cycle-related control signals representative of directions to pulse-width modulate the clock of the computer with such duty cycle.

A personal computer comprising:

• provision for user input;
• a memory;
• provision for user output;
• a microprocessor coupled to said provision for user input, said memory, and said provision for user output;
• a plurality of sampling circuits responsive to different system activity levels and producing system activity signals representative of said system activity levels;
• circuitry responsive to said system activity signals and supplying weighted activity output signals adjustably weighting said system activity levels;
• and
• filter circuitry responsive to said weighted activity output signals to produce a series of duty-cycle-related control signals representative of directions to pulse-width modulate a clock of said computer.

A personal computer comprising:

• an input device;
• a memory;
• a display;
• a peripheral processing unit (PPU) having a plurality of peripheral event counting circuits responsive to different system activity levels and producing system activity signals representative of said system activity levels, said PPU further having a variable pulse width generator supplying pulses with a duty cycle established by duty cycle control data input thereto;
• and
• a microprocessor unit (MPU) coupled to said input device, said memory, and said display, said MPU having circuitry responsive to said system activity signals, said circuitry supplying weighted activity output signals by adjustably weighting said system activity levels and said circuitry supplying, by filtering in response to said weighted activity output signals, a series of said duty cycle control data to said variable pulse width generator, said MPU further comprising a clock circuit having an input connected to receive said pulses from said variable pulse width generator in said PPU.

An electronic wiring board article of manufacture comprising:

• a printed wiring board having a substantially insulative planar board element, conductors in or on said board element;
• and
• a first integrated circuit mounted on said printed wiring board said first integrated circuit comprising:
• a peripheral processing unit (PPU) having a plurality of peripheral event counting circuits responsive to different system activity levels and producing system activity signals representative of the system activity levels, said PPU further having a variable pulse width generator supplying pulses with a duty cycle established by duty cycle control data input thereto;
• a second integrated circuit mounted on said printed wiring board said second integrated circuit comprising:
• a microprocessor unit (MPU) coupled to said input device, said memory, and said display, said MPU having circuitry responsive to said system activity signals, said circuitry supplying weighted activity output signals by adjustably weighting said system activity levels and supplying, by filtering in response to said weighted activity output signals, a series of said duty cycle control data to said variable pulse width generator, said MPU further comprising a clock circuit having an input connected to receive said pulses from said variable pulse width generator in said PPU;
• and said conductors of said printed wiring board comprising one or more conductors connecting said first integrated circuit to said second integrated circuit.