G06F 9/3001
Arithmetic instructions
Official title: {Arithmetic instructions}
G06F9/3001 (Arithmetic instructions) appears on 3,855 US grants and 4,069 published applications in this corpus.
Search patents in G06F- Granted patents
- 3,855
- Published applications
- 4,069
- Assignees
- 686
- Inventors
- 5,083
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 3 | 0 |
| 1982 | 1 | 0 |
| 1983 | 5 | 0 |
| 1984 | 7 | 0 |
| 1985 | 1 | 0 |
| 1986 | 7 | 0 |
| 1987 | 5 | 0 |
| 1988 | 7 | 0 |
| 1989 | 8 | 0 |
| 1990 | 5 | 0 |
| 1991 | 8 | 0 |
| 1992 | 7 | 0 |
| 1993 | 12 | 0 |
| 1994 | 22 | 0 |
| 1995 | 17 | 0 |
| 1996 | 35 | 0 |
| 1997 | 46 | 0 |
| 1998 | 87 | 0 |
| 1999 | 88 | 0 |
| 2000 | 73 | 0 |
| 2001 | 70 | 17 |
| 2002 | 53 | 58 |
| 2003 | 51 | 64 |
| 2004 | 49 | 101 |
| 2005 | 42 | 80 |
| 2006 | 55 | 74 |
| 2007 | 53 | 69 |
| 2008 | 71 | 116 |
| 2009 | 61 | 94 |
| 2010 | 75 | 62 |
| 2011 | 87 | 74 |
| 2012 | 67 | 58 |
| 2013 | 82 | 136 |
| 2014 | 82 | 147 |
| 2015 | 101 | 123 |
| 2016 | 153 | 149 |
| 2017 | 167 | 195 |
| 2018 | 153 | 217 |
| 2019 | 212 | 332 |
| 2020 | 256 | 335 |
| 2021 | 269 | 296 |
| 2022 | 286 | 313 |
| 2023 | 286 | 259 |
| 2024 | 289 | 237 |
| 2025 | 219 | 224 |
| 2026 | 116 | 239 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Systems, methods, and apparatuses for heterogeneous computing29 Sep 2026US 12,748,618 B2Intel Corporation
- Backward compatibility testing of software in a mode that attempts to induce skew15 Sep 2026US 12,737,282 B2Sony Interactive Entertainment Inc.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Cache structure and utilization15 Sep 2026US 12,737,318 B2Intel Corporation
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Efficient matrix multiply and add with a group of warps1 Oct 2026US 2026/0299943 A1NVIDIA Corporation
- Quantized flash attention1 Oct 2026US 2026/0299946 A1Tesla, Inc.
- Cache system and method for processing cache1 Oct 2026US 2026/0299950 A1Fujitsu Limited
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
Most cited
By later US patents
- Method and system for efficient matrix multiplication in a SIMD processor architecture531US 7,873,812 B12011
- Algorithm mapping, specialized instructions and architecture features for smart memory computing432US 7,546,438 B22009
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements418US 7,447,720 B2Micron Technology, Inc. · 2008
- Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture418US 8,555,037 B2Apple Inc. · 2013