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US 2026/0299950 A1Published application
Cache system and method for processing cache
AssigneeFujitsu Limited
InventorTakahito HIRANO
Life of this patent
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Abstract
According to an aspect of the embodiment, the cache system includes a first arithmetic processing device that includes an internal cache and that determines whether data related to an atomic instruction or an exclusive instruction is hit in the internal cache, and a second arithmetic processing device that includes a Last-Level-Cache (LLC) and that executes the atomic instruction using the data stored in the LLC or executes an exclusive process related to the exclusive instruction when the data is not hit in the internal cache.
Claims10
A cache system comprising:
- a first arithmetic processing device that comprises an internal cache and that determines whether data related to an atomic instruction or an exclusive instruction is hit in the internal cache;
- and
- a second arithmetic processing device that comprises a Last-Level-Cache (LLC) and that executes the atomic instruction using the data stored in the LLC or executes an exclusive process related to the exclusive instruction when the data is not hit in the internal cache.
A computer-implemented method for processing a cache, the method comprising:
- in a first arithmetic processing device that comprises an internal cache, determining whether data related to an atomic instruction or an exclusive instruction is hit in the internal cache;
- and
- in a second arithmetic processing device that comprises a Last-Level-Cache (LLC), executing the atomic instruction by using the data stored in the LLC or executing an exclusive process related to the exclusive instruction when the data is not hit (found) in the internal cache.
Dependencies are inferred from the claim text.