G06F 5/015
Having at least two separately controlled shifting levels
Official title: {having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence)}
G06F5/015 (Having at least two separately controlled shifting levels) appears on 227 US grants and 96 published applications in this corpus.
Search patents in G06F- Granted patents
- 227
- Published applications
- 96
- Assignees
- 97
- Inventors
- 322
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 5 | 0 |
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 3 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 3 | 0 |
| 1985 | 4 | 0 |
| 1986 | 3 | 0 |
| 1987 | 4 | 0 |
| 1988 | 2 | 0 |
| 1989 | 11 | 0 |
| 1990 | 6 | 0 |
| 1991 | 5 | 0 |
| 1992 | 10 | 0 |
| 1993 | 1 | 0 |
| 1994 | 4 | 0 |
| 1995 | 8 | 0 |
| 1996 | 5 | 0 |
| 1997 | 5 | 0 |
| 1998 | 4 | 0 |
| 1999 | 15 | 0 |
| 2000 | 13 | 0 |
| 2001 | 13 | 0 |
| 2002 | 2 | 8 |
| 2003 | 6 | 5 |
| 2004 | 5 | 4 |
| 2005 | 4 | 0 |
| 2006 | 4 | 6 |
| 2007 | 4 | 3 |
| 2008 | 4 | 5 |
| 2009 | 4 | 3 |
| 2010 | 2 | 4 |
| 2011 | 4 | 3 |
| 2012 | 4 | 3 |
| 2013 | 3 | 2 |
| 2014 | 5 | 5 |
| 2015 | 3 | 1 |
| 2016 | 3 | 1 |
| 2017 | 1 | 3 |
| 2018 | 8 | 10 |
| 2019 | 5 | 4 |
| 2020 | 6 | 6 |
| 2021 | 4 | 3 |
| 2022 | 2 | 2 |
| 2023 | 4 | 6 |
| 2024 | 3 | 3 |
| 2025 | 2 | 3 |
| 2026 | 4 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Fast matrix multiplication6 Oct 2026US 12,754,970 B2
- Low latency matrix multiply unit24 Feb 2026US 12,561,395 B2Google Inc.
- FPGA wide barrel-shifters implementation using packed DSP multipliers27 Jan 2026US 12,536,019 B2Microsoft Technology Licensing, LLC
- Low latency matrix multiply unit20 Jan 2026US 12,530,426 B2Google Inc.
- Compute optimizations for neural networks30 Sep 2025US 12,430,131 B2Intel Corporation
- Fpga wide barrel-shifters implementation using packed dsp multipliers14 May 2026US 2026/0133797 A1Microsoft Technology Licensing, LLC
- Systems and methods for artificial intelligence computations7 May 2026US 2026/0126955 A1Samsung Electronics Co., Ltd.
- Compute optimizations for neural networks19 Feb 2026US 2026/0050438 A1Intel Corporation
- Low latency matrix multiply unit17 Jul 2025US 2025/0232001 A1Google Inc.
- Low latency matrix multiply unit17 Jul 2025US 2025/0232003 A1Google Inc.
Most cited
By later US patents
- Devices and methods with programmable logic and digital signal processing regions256US 6,538,470 B1Altera Corporation · 2003
- High speed image processing computer with overlapping windows-div236US 5,146,592 AVisual Information Technologies, Inc. · 1992
- High speed image processing system using separate data processor and address generator229US 4,985,848 AVisual Information Technologies, Inc. · 1991
- Convolution memory126US 5,014,235 A1991
- Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor123US 5,761,726 ATexas Instruments Incorporated · 1998