Low latency matrix multiply unit
AssigneeGoogle Inc.
InventorsAndrew Everett Phelps, Norman Paul Jouppi
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Abstract
Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. The matrix multiply unit may include cells arranged in columns of the systolic array. Two chains of weight shift registers per column of the systolic array are in the matrix multiply unit. Each weight shift register is connected to only one chain and each cell is connected to only one weight shift register. A weight matrix register per cell is configured to store a weight input received from a weight shift register. A multiply unit is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.
Claims18
(canceled)
A processor comprising:
- a processing core having an array of cells;
- a plurality of first shift chains, each first shift chain arranged along rows of the array of cells;
- a plurality of second shift chains, each second shift chain arranged along columns of the array of cells, and
- wherein each cell of the array of cells is coupled to a respective multiplexor that is configurable to control whether the cell receives a weight from a first shift chain arranged along a row of the cell or from a second shift chain arranged along a column of the cell,
- wherein the processor is configured to execute instructions that cause the processor to perform operations comprising:
- concurrently two loading weight values on each cycle using the plurality of first shift chains and the plurality of second shift chains.
Dependencies are inferred from the claim text.