Low latency matrix multiply unit

A method performed by a processor, wherein the processor comprises a processing core having an array of cells, a first plurality of shift chains, and a second plurality of shift chains, the method comprising:

• selectively loading weight values using the first plurality of shift chains corresponding to the rows of the array of cells or using the second plurality of shift chains corresponding to the columns of the array of cells;
• and
• performing one or more matrix multiplication operations using the loaded weight values and a vector input.

A non-transitory computer program product storing instructions that, when executed by a programmable processor comprising a processing core having an array of cells, a first plurality of shift chains, and a second plurality of shift chains, cause the processor to perform operations comprising:

• selectively loading weight values using the first plurality of shift chains corresponding to the rows of the array of cells or using the second plurality of shift chains corresponding to the columns of the array of cells;
• and
• performing one or more matrix multiplication operations using the loaded weight values and a vector input.