Low latency matrix multiply unit
AssigneeGoogle Inc.
InventorsAndrew Everett Phelps, Norman Paul Jouppi
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Abstract
Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. The matrix multiply unit may include cells arranged in columns of the systolic array. Two chains of weight shift registers per column of the systolic array are in the matrix multiply unit. Each weight shift register is connected to only one chain and each cell is connected to only one weight shift register. A weight matrix register per cell is configured to store a weight input received from a weight shift register. A multiply unit is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.
Claims29
A processor comprising:
- a processing core having an array of cells;
- a first plurality of shift chains coupled to even-numbered rows or columns of the array of cells;
- a second plurality of shift chains coupled to odd-numbered rows or columns of the array of cells, wherein the processor is configured to execute instructions that cause the processor to perform operations comprising:
- concurrently loading two weight values on each cycle into each row or column using the first plurality of shift chains and the second plurality of shift chains.
A method performed by a processor having a processing core with an array of cells, the method comprising:
- concurrently loading two weight values on each cycle into each row or column of the array of cells using a first plurality of shift chains coupled to even-numbered rows or columns of the array of cells and a second plurality of shift chains coupled to odd-numbered rows or columns of the array of cells.
Dependencies are inferred from the claim text.