High speed image processing system using separate data processor and address generator

An image processing system, comprising:

• a memory operable to store image pixel data;
• an address generator for generating memory addresses for reading from and writing to said memory;
• a data processor operable independently of said address generator for processing pixel data and for supplying pixel data to said memory;
• and circuitry for programmably controlling said address generator and said data processor in a synchronized manner such that independent instruction words may be simultaneously generated for the address generator and the data processor, said circuitry for programmably controlling the address generator including a writable control store associated with said address generator for providing said instruction words associated with the address generator, a writable control store associated with said data processor for providing instruction words associated with said data processor and an instruction sequencer for addressing said control stores, such that a single address may generate instructions for both the address generator and the data processor.

The method of processing pixel data in an image processing system, comprising the steps of:

• storing pixel data representative of an image in a memory frame store comprising a plurality of memory areas;
• accessing desired pixels from said memory frame store with a programmable address generator connected to said memory frame store;
• processing pixel data from said memory area with respective programmable data processors;
• synchronously supplying instructions to said address generator to generate memory addresses for accessing desired pixels stored in said frame store;
• supplying instructions to said data processors for processing pixels accessed by said address generator to produce a desired effect on said image;
• and
• passing flag information on a flag bus connected between address generator and said data processors.

An image processing system, comprising:

• an image memory for storing pixel data representative of an image, said memory having an input/output data port;
• circuitry for addressing said memory to read and write said pixel data;
• a data processor for processing said pixel data, said processor including a plurality of pixel processing units, each said unit having a data input port and a data output port;
• a register file connected to said data input/output port of said data processor for providing temporary storage for said pixel data;
• a pair of buses connected to respective said input and output ports of said pixel processing units so that pixel data can be repeatedly input and output from said processing units via said buses and via said register file;
• and
• circuitry for controlling the pixel processing units to process said pixel data.

An image processing system, comprising:

• an image memory for storing image data, said memory including at least one video DRAM having a random access memory section accessible by an address port and a data input/output port, said video DRAM further including a serial pixel storage section and circuitry for loading said serial register section with image data from said random access section, said serial storage section being coupled to a serial data output port of said video DRAM;
• an address processor coupled to said video DRAM address port for accessing said random access memory section;
• a data processor coupled to said video DRAM data input/output port for processing image data read from said random access memory section and for writing processed data to said random access memory section;
• and
• a pixel processor coupled to said serial data output port for receiving serial pixel data and for coupling said serial pixel data to an output of said pixel processor, said pixel processor further including timing means for clocking said serial storage section to provide a serial output of said pixels.