US 5,014,235 A · Convolution memory

Abstract

Method and apparatus including a system of integrated ciruit devices for executing matrix operations of the form [A] operated upon by [B] equals [C], where [A], [B] and [C] are each a matrix having a plurality of elements expressed in either unsigned or in two's complement format. The system includes at least one first array of data storage means organized as (j) physical rows and (k) physical columns of bits for providing storage for one bit of each of a plurality of elements of a row vectors of the matrix [A], an individual one of the (j) rows having bits of the same binary weight. The system further includes at least one second array of data storage means organized as (m) physical rows and (n) physical columns of bits, an individual one of the (m) rows storing a same binary weight bit or each of a plurality of elements of a column vector of the matrix [B]. The system further includes a processing device for processing in a predetermined manner a specified one of the (j) rows of the first array of data storage means with a specified one of the (m) rows of the second array of data storage means for producing a plurality of (x) output bits. The system also includes logic for determining a number of the output bits having a specified logic state and logic for determining a dot product.

A convolution memory chip comprising:

a matrix memory, the matrix memory comprising:
(a) matrix memory row address logic (1221), having a matrix address input, a matrix address control input, a matrix row address latch (1311) having an input coupled to the matrix address input and controlled by the matrix address control input for storing a matrix row address presented on the matrix address input, a matrix row address decoder (1313) having a plurality (R) of matrix row select outputs, the matrix row address decoder being coupled to the matrix row address latch and operable for activating one of the R matrix row select outputs in response to a content of the matrix address latch;
(b) a matrix memory cell array (1220), comprising a matrix of R rows by C columns of memory cells, the matrix memory cell array having matrix column buses coupled thereto, the matrix memory cell array being coupled to the R matrix row select outputs and responsive to an activation of one of the R matrix row select outputs for coupling each memory cell an associated one of the R rows to an associated one of the matrix column buses,
(c) matrix memory column sense amplifiers and read/write logic (1223) coupled to the matrix memory cell array through the matrix column buses and having a matrix data port for receiving and transmitting matrix data to means external to the convolution memory chip, logic (1223) further having an input for receiving the matrix column buses and producing in response to information conveyed by the matrix column buses C signals upon a matrix memory bus, logic (1223) further having having a column decoder (1354) coupled to the matrix address and responsive to a matrix column address being input thereon for decoding the matrix column address and asserting a corresponding matrix column select signal for selecting a memory cell corresponding to the row address latched in the matrix row address latch, the operation of the column decoder causing a transfer of N bits of information between the selected row of the matrix memory cell array and the matrix data port,
a buffer memory, the buffer memory comprising:
(d) buffer memory row logic (1232) having a buffer address input coupled to a buffer address, a buffer address control input, a buffer row address latch (1511) coupled to the buffer address input and controlled by the buffer address control input for latching a buffer row address appearing on the buffer address, a buffer row address decoder (1513) having an input coupled to an output of the buffer row address latch and responsive to a buffer row address latched therein for activating one of a plurality (V) of buffer row select outputs of the decoder,
(e) a transpose buffer memory cell array (1231), comprising a matrix of V rows by T columns of memory cells, the transpose buffer memory cell array having buffer memory column buses coupled thereto, and, in response to an activation of one of the V buffer row select outputs, connecting each memory cell in an associated one of the V rows to an associated buffer memory column bus for transferring W bits of information between one column of the buffer memory cell array and a buffer data port,
(f) buffer memory column sense amplifiers and read/write logic (1229) having an input coupled to the buffer address and responsive to a buffer column address appearing thereon for selecting a column of the buffer memory cell array for transferring information between the buffer data port and the buffer memory cell array, and also for receiving the buffer column bus and producing in response to signals appearing thereon T signals upon a buffer memory bus,
the convolution memory chip further comprising processor logic, the processor logic being coupled between the matrix memory bus and the buffer memory bus and comprising:
(g1) processor logic cells (1225) coupled to the matrix memory bus and to the buffer memory bus for performing operations upon data received from the matrix memory bus and the buffer memory bus, the processor logic cells having an output coupled to a processor cell bus for expressing thereon data resulting from the operations, and
(g2) global logic (1227), coupled to and receiving the processor cell bus for performing operations upon the data received from the processor cell bus and producing an output expressive of the performed operations.

8 more elements

Convolution memory

Life of this patent

Convolution memory

Life of this patent

Abstract

Claims20