US 12,536,019 B2 · FPGA wide barrel-shifters implementation using packed DSP multipliers

Abstract

Barrel-shifters may be implemented in field programmable gate array (FPGA) using digital signal processor (DSP) multipliers, rather than consuming lookup table (LUT) resources. This advantageously uses otherwise under-utilized assets, leaving previously heavily-burdened LUT resources available for other uses. Building blocks of 8-bit and 4-bit DSP-based shifters are implemented in parallel sets for wide data and in tandem stages for larger shifts. For example, a 32-bit barrel-shifter may be implemented using a set of seven (7) parallel 8-bit shifters to handle the width of the data in a first stage and another set of eight (8) parallel 4-bit shifters in a second stage that operates in tandem with the first stage, to complete the shift. In an example, the first stage provides fine shifting and the second stage provides coarse shifting. To achieve even wider barrel-shifters, for example a 256-bit shifter, 32-bit barrel-shifter may be used recursively.

Claims22

Dependent claims

A system comprising:

a barrel-shifter operable to align a processed packet header into an aligned, processed packet header for attachment to a packet payload, the barrel-shifter comprising:
a first shift stage comprising:
a first one-hot decoder operable to convert a first binary shift value into a first one-hot shift value;
and
a first L-by-M (L×M) multiplier operable to multiply a first portion of an operand by the first one-hot shift value, wherein the first portion of the operand comprises at least a portion of M least significant bits of the operand;
and
a second shift stage comprising:
a second one-hot decoder operable to convert a second binary shift value into a second one-hot shift value, wherein the first binary shift value comprises least significant bits of a total binary shift value and wherein the second shift value comprises more significant bits of the total binary shift value than bits of the first binary shift value;
and
a first N-by-P (N×P) multiplier operable to multiply at least a portion of P most significant bits of an output of the first L×M multiplier by the second one-hot shift value.

7 more elements

A computer-implemented method comprising a barrel-shifting process, the barrel-shifting process performed by a barrel-shifter operable to align a processed packet header into an aligned, processed packet header for attachment to a packet payload, the method comprising:

converting, by the barrel-shifter, a first binary shift value into a first one-hot shift value;
multiplying, by the barrel-shifter using a first L-by-M (L×M) multiplier, a first portion of an operand by the first one-hot shift value, wherein the first portion of the operand comprises at least a portion of M least significant bits of the operand;
converting, by the barrel-shifter, a second binary shift value into a second one-hot shift value, wherein the first binary shift value comprises least significant bits of a total binary shift value and wherein the second binary shift value comprises more significant bits of the total binary shift value than bits of the first binary shift value;
and
multiplying, by the barrel-shifter using a first N-by-P (N×P) multiplier, at least a portion of P most significant bits of an output of the first L×M multiplier by the second one-hot shift value.

2 more elements

A system comprising:

a bus aligner comprising:
a bus-shifter comprising a barrel shifter operable to align a processed packet header into an aligned, processed packet header for attachment to a packet payload;
control logic;
and
a latchable register;
wherein the control logic is operable to determine a total binary shift value to be performed by the bus-shifter;
wherein the latchable register is operable to store an output of the bus-shifter;
and
wherein the barrel shifter comprises:
a first shift stage comprising:
a first one-hot decoder operable to convert a first binary shift value into a first one-hot shift value;
and
a first L-by-M (L×M) multiplier operable to multiply a first portion of an operand by the first one-hot shift value, wherein the first portion of the operand comprises at least a portion of M least significant bits of the operand;
and
a second shift stage comprising:
a second one-hot decoder operable to convert a second binary shift value into a second one-hot shift value, wherein the first binary shift value comprises least significant bits of the total binary shift value and wherein the second binary shift value comprises more significant bits of the total binary shift value than bits of the first binary shift value;
and
a first N-by-P (N×P) multiplier operable to multiply at least a portion of P most significant bits of an output of the first L×M multiplier by the second one-hot shift value.

15 more elements

Dependencies are inferred from the claim text.

FPGA wide barrel-shifters implementation using packed DSP multipliers

Life of this patent

FPGA wide barrel-shifters implementation using packed DSP multipliers

Life of this patent

Abstract

Claims22