Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor

A multi-processing system comprising:

• a plurality of m memories, each of said m memories having a unique addressable memory portion fixed upon manufacture within a single memory address space;
• a plurality of n processors, where n is less than m and each of said n processors has a parameter memory having a corresponding fixed parameter memory base address within said single memory address space and a predetermined plurality of corresponding data memories, said predetermined plurality of data memories corresponding to each processor having a corresponding fixed data memory base address within said single memory address space, each of said processors capable of generating any address within said single memory address space for read/write access to data stored within said plurality of m memories in accordance with received instructions, a parameter memory base address instruction executing on any one of said plurality of n processors generating said parameter memory base address of said parameter memory corresponding to said one processor and a data memory base address instruction executing on any one of said plurality of n processors generating said data memory base address of said predetermined plurality of data memories corresponding to said one processor;
• a switch matrix connected to said plurality of m memories and said plurality of n processors responsive to an address generated by said processors to selectively route data between a one of said plurality of n processors and a one of said plurality of m memories whose unique addressable memory portion encompasses said address.