G06F 12/1063
The data cache being concurrently virtually addressed
Official title: {the data cache being concurrently virtually addressed}
G06F12/1063 (The data cache being concurrently virtually addressed) appears on 496 US grants and 469 published applications in this corpus.
Search patents in G06F- Granted patents
- 496
- Published applications
- 469
- Assignees
- 102
- Inventors
- 824
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 2 | 0 |
| 1985 | 2 | 0 |
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 7 | 0 |
| 1989 | 3 | 0 |
| 1990 | 2 | 0 |
| 1991 | 3 | 0 |
| 1992 | 4 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 3 | 0 |
| 1996 | 3 | 0 |
| 1997 | 4 | 0 |
| 1998 | 5 | 0 |
| 1999 | 6 | 0 |
| 2000 | 4 | 0 |
| 2001 | 4 | 0 |
| 2002 | 6 | 7 |
| 2003 | 6 | 6 |
| 2004 | 5 | 8 |
| 2005 | 6 | 5 |
| 2006 | 3 | 9 |
| 2007 | 3 | 7 |
| 2008 | 5 | 0 |
| 2009 | 1 | 8 |
| 2010 | 6 | 7 |
| 2011 | 7 | 2 |
| 2012 | 5 | 5 |
| 2013 | 11 | 13 |
| 2014 | 8 | 9 |
| 2015 | 14 | 19 |
| 2016 | 14 | 14 |
| 2017 | 13 | 11 |
| 2018 | 10 | 31 |
| 2019 | 30 | 59 |
| 2020 | 44 | 25 |
| 2021 | 26 | 31 |
| 2022 | 36 | 85 |
| 2023 | 51 | 35 |
| 2024 | 63 | 37 |
| 2025 | 45 | 20 |
| 2026 | 15 | 16 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System, method, and computer readable medium for capability-enhanced virtualization of caches6 Oct 2026US 12,754,856 B2University of Virginia Patent Foundation
- System and method for facilitating dynamic command management in a network interface controller (NIC)6 Oct 2026US 12,754,857 B2Hewlett Packard Enterprise Development LP
- Disaggregated hypervisor25 Aug 2026US 12,717,711 B1NVIDIA Corporation
- Page table entry caches with multiple tag lengths18 Aug 2026US 12,711,076 B2SiFive, Inc.
- Fat tree adaptive routing11 Aug 2026US 12,705,190 B2Hewlett Packard Enterprise Development LP
- Hardware-Assisted Dynamic Register Allocation8 Oct 2026US 2026/0310610 A1MIPS Tech, LLC
- Prefetch circuitry for page table entry streaming1 Oct 2026US 2026/0300185 A1Intel Corporation
- Electronic device including device-dedicated and host memory regions10 Sep 2026US 2026/0267806 A1XCENA Inc.
- Address translation prefetching for input/output devices10 Sep 2026US 2026/0267807 A1Microsoft Technology Licensing, LLC
- Page request interface support in handling pointer fetch with caching host memory address translation data16 Jul 2026US 2026/0203230 A1Micron Technology, Inc.
Most cited
By later US patents
- Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations181US 4,456,954 AInternational Business Machines Corporation · 1984
- Memory management and protection system for virtual memory in computer system173US 5,890,189 AKabushiki Kaisha Toshiba · 1999
- Memory access controller171US 4,669,043 ASignetics Corporation · 1987
- Variable address mode cache135US 4,797,814 AInternational Business Machines Corporation · 1989
- Integrated processing and L2 DRAM cache127US 5,895,487 AInternational Business Machines Corporation · 1999