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US 12,711,076 B2Granted
Page table entry caches with multiple tag lengths
AssigneeSiFive, Inc.
InventorsPerrine Peresse, Shubhendu Sekhar Mukherjee, Krste Asanovic
Life of this patent
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Abstract
Systems and methods are disclosed for page table entry caches with multiple tag lengths. For example, an integrated circuit (e.g., a processor) includes a page table walk circuitry including a page table entry cache, in which the page table walk circuitry is configured to access a multi-level page table, and in which a first entry of the page table entry cache combines a first number of multiple levels and a second entry of the page table entry cache combines a second number of multiple levels that is different from the first number of multiple levels.
Claims16
An integrated circuit comprising:
- a page table walk circuitry including a page table entry cache, wherein the page table walk circuitry is configured to access a first multi-level page table that encodes a first stage address translation in a two-stage address translation, wherein a first entry of the page table entry cache includes a first tag and combines a first number of multiple levels, wherein a second entry of the page table entry cache includes a second tag and combines a second number of multiple levels that is different from the first number of multiple levels, wherein at least one of the first tag or the second tag are used checking the page table entry cache, wherein the first tag includes a translation tag that indicates a privilege level, a virtualization mode, and a translation mode;
- wherein the page table walk circuitry is further configured to:
- check the page table entry cache for a guest virtual address using multiple tag lengths corresponding to overlapping subsets of the guest virtual address;
- responsive to finding a tag matching a subset of the guest virtual address, access a guest physical address that is stored in an entry of the page table entry cache corresponding to the tag matching a subset of the guest virtual address;
- check the page table entry cache for the guest physical address using multiple tag lengths corresponding to overlapping subsets of the guest physical address;
- responsive to finding a tag matching a subset of the guest physical address, access a first system physical address that is stored in an entry of the page table entry cache corresponding to the tag matching a subset of the guest physical address;
- determine a second system physical address as a translation of the guest physical address by continuing a page table walk of the first multi-level page table using the first system physical address pointing to a page table in the first multi-level page table;
- and
- continue a page table walk of a second multi-level page table using the second system physical address pointing to a page table in the second multi-level page table.
6 more elements
A method comprising:
- receiving an address translation request including a guest virtual address;
- checking a page table entry cache for the guest virtual address using multiple tag lengths corresponding to overlapping subsets of the guest virtual address;
- responsive to finding a tag matching a subset of the guest virtual address, accessing a guest physical address that is stored in an entry of the page table entry cache corresponding to the tag matching a subset of the guest virtual address;
- checking the page table entry cache for the guest physical address using multiple tag lengths corresponding to overlapping subsets of the guest physical address;
- responsive to finding a tag matching a subset of the guest physical address, accessing a first system physical address that is stored in an entry of the page table entry cache corresponding to the tag matching a subset of the guest physical address;
- determining a second system physical address as a translation of the guest physical address by continuing a page table walk of a first multi-level page table using the first system physical address pointing to a page table in the first multi-level page table;
- and
- continuing a page table walk of a second multi-level page table using the second system physical address pointing to a page table in the second multi-level page table to determine a third system physical address as a translation of the guest virtual address.
5 more elements
A non-transitory computer readable medium storing instructions, that upon execution, cause operations comprising:
- receiving an address translation request including a guest virtual address;
- checking a page table entry cache for the guest virtual address using multiple tag lengths corresponding to overlapping subsets of the guest virtual address;
- responsive to finding a tag matching a subset of the guest virtual address, accessing a guest physical address that is stored in an entry of the page table entry cache corresponding to the tag matching a subset of the guest virtual address;
- checking the page table entry cache for the guest physical address using multiple tag lengths corresponding to overlapping subsets of the guest physical address;
- responsive to finding a tag matching a subset of the guest physical address, accessing a first system physical address that is stored in an entry of the page table entry cache corresponding to the tag matching a subset of the guest physical address;
- determining a second system physical address as a translation of the guest physical address by continuing a page table walk of a first multi-level page table using the first system physical address pointing to a page table in the first multi-level page table;
- and
- continuing a page table walk of a second multi-level page table using the second system physical address pointing to a page table in the second multi-level page table to determine a third system physical address as a translation of the guest virtual address.
5 more elements
Dependencies are inferred from the claim text.