Prefetch circuitry for page table entry streaming

A method comprising:

• issuing, by an execution circuit, a memory access request comprising a virtual address;
• sending a request, by a page miss handler based on a miss of the virtual address in a translation lookaside buffer comprising a plurality of virtual address to physical address mappings, to a data structure for multiple level paging that stores a cache line that includes a page table entry to indicate a physical address for the virtual address of the memory access request;
• filling, by the page miss handler, the physical address for the virtual address into the translation lookaside buffer;
• and
• causing, by a prefetch circuit based on the miss of the virtual address in the translation lookaside buffer, a store of at least one other cache line of page table entries into a cache from the data structure for multiple level paging that stores the cache line.

A system comprising:

• a system memory;
• a cache;
• an execution circuit to generate a memory access request comprising a virtual address;
• a page miss handler to, based on a miss of the virtual address in a translation lookaside buffer comprising a plurality of virtual address to physical address mappings, send a request to a data structure for multiple level paging in the system memory that stores a cache line that includes a page table entry to indicate a physical address for the virtual address of the memory access request, and fill the physical address for the virtual address into the translation lookaside buffer;
• and
• a prefetch circuit to, based on the miss of the virtual address in the translation lookaside buffer, cause a store of at least one other cache line of page table entries into the cache from the data structure for multiple level paging that stores the cache line.