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AssigneeInternational Business Machines Corporation
InventorsRobert J. Bullions, III, Thomas O. Curlee, III, Peter H. Gum, Bruce L. McGilvray, Ethel L. Richardson
Estimating the term…
Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.
In a data processing system having at least one central processor (CP) and a main storage (MS) for supporting a host control program and at least one guest control program, the CP including an instruction execution (IE) unit for executing instructions and generating real or virtual address requests for accesses in main storage or a cache for host or guest programs, a hardware translation lookaside buffer (TLB) having a plurality of addressable entries, each TLB entry containing a validity flag field, a STO (segment table origin) field, a virtual address field and an absolute address field, the system comprising:
In a data processing system haivng at least one central processor (CP) and a main storage (MS) for supporting at least one guest virtual machine (VM), the CP including an instruction execution (IE) unit for executing instructions and generating real or virtual address requests for accesses in main storage or a cache, dynamic address translation (DAT) means, a hardware address translation lookaside buffer (TLB) having a plurality of entries, each TLB entry capable of containing an address translation including a validate field, a STO (segment table origin) field, a virtual address field and an absolute address field, DAT mode indicating means in the CP being controlled by a current PSW (program status word) in the CP, the CP also comprising:
Dependencies are inferred from the claim text.