Memory access controller

Data processing system comprising a processor connected to a common address bus, a memory hierarchy comprising at least a cache memory and a local memory connected to the common bus, a memory access controller connected to the common bus and via a cache address bus to the cache memory, which memory access controller comprises:

• a cache controller which comprises a first storage unit for storing first indicators which indicate data present in the cache memory, a first check unit connected to said first storage unit and having a first address input connected to said processor for receiving virtual addresses supplied by the processor, said first check unit being provided for checking a received virtual address to determine if said virtual address corresponds to one of said first indicators stored in said first storage unit and for generating a first check result signal upon correspondence and a second check result signal upon non-correspondence, said cache controller being further provided with a first enabling unit for enabling the access to the cache memory, which first enabling unit being activated upon receiving the first check result signal;
• a translation unit having a second address input for receiving virtual addresses and being provided for translating virtual addresses into physical addresses, said translation unit comprises a second storage unit for storing second indicators which indicate data present in the local memory, a second check unit connected to said storage unit and to said second address input and being provided for checking a received virtual address to determine if said virtual address corresponds to one of said second indicators stored in said second storage unit and for generating a third check result signal upon correspondence and a fourth check result signal upon non-correspondence, said translation unit being controlled by said second check result signal supplied at a first control input thereof, said translation unit being further provided with a second enabling unit for enabling the access to a local memory, which second enabling unit being activated upon receiving a third check result signal;
• said cache controller by means of its first input and the translation unit by means of its second address input being connected in parallel to an address bus which is connected to a virtual address output of the processor, which address bus being provided for transporting the virtual addresses simultaneously to said cache controller and said translation unit.