G06F 12/1027
Using associative or pseudo-associative address translation means
Official title: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F12/1027 (Using associative or pseudo-associative address translation means) appears on 4,483 US grants and 4,014 published applications in this corpus.
Search patents in G06F- Granted patents
- 4,483
- Published applications
- 4,014
- Assignees
- 544
- Inventors
- 6,137
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 4 | 0 |
| 1977 | 4 | 0 |
| 1978 | 9 | 0 |
| 1979 | 3 | 0 |
| 1980 | 2 | 0 |
| 1981 | 2 | 0 |
| 1982 | 5 | 0 |
| 1983 | 11 | 0 |
| 1984 | 16 | 0 |
| 1985 | 8 | 0 |
| 1986 | 15 | 0 |
| 1987 | 15 | 0 |
| 1988 | 25 | 0 |
| 1989 | 18 | 0 |
| 1990 | 22 | 0 |
| 1991 | 19 | 0 |
| 1992 | 21 | 0 |
| 1993 | 28 | 0 |
| 1994 | 36 | 0 |
| 1995 | 56 | 0 |
| 1996 | 49 | 0 |
| 1997 | 43 | 0 |
| 1998 | 76 | 0 |
| 1999 | 86 | 0 |
| 2000 | 53 | 0 |
| 2001 | 58 | 10 |
| 2002 | 74 | 64 |
| 2003 | 67 | 53 |
| 2004 | 73 | 91 |
| 2005 | 62 | 78 |
| 2006 | 72 | 104 |
| 2007 | 67 | 91 |
| 2008 | 77 | 109 |
| 2009 | 72 | 129 |
| 2010 | 100 | 111 |
| 2011 | 102 | 97 |
| 2012 | 134 | 98 |
| 2013 | 132 | 122 |
| 2014 | 135 | 236 |
| 2015 | 155 | 159 |
| 2016 | 221 | 235 |
| 2017 | 227 | 240 |
| 2018 | 220 | 258 |
| 2019 | 277 | 328 |
| 2020 | 293 | 263 |
| 2021 | 231 | 217 |
| 2022 | 247 | 262 |
| 2023 | 232 | 199 |
| 2024 | 232 | 196 |
| 2025 | 212 | 166 |
| 2026 | 85 | 98 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- System, method, and computer readable medium for capability-enhanced virtualization of caches6 Oct 2026US 12,754,856 B2University of Virginia Patent Foundation
- System and method for facilitating dynamic command management in a network interface controller (NIC)6 Oct 2026US 12,754,857 B2Hewlett Packard Enterprise Development LP
- Multi-core processor-based system implementing directed page table entry invalidation29 Sep 2026US 12,748,705 B2Ampere Computing LLC
- Address range based memory hints for prefetcher, cache and memory controller22 Sep 2026US 12,743,378 B2Google Inc.
- Backward compatibility testing of software in a mode that attempts to induce skew15 Sep 2026US 12,737,282 B2Sony Interactive Entertainment Inc.
- Hardware-Assisted Dynamic Register Allocation8 Oct 2026US 2026/0310610 A1MIPS Tech, LLC
- Prefetch circuitry for page table entry streaming1 Oct 2026US 2026/0300185 A1Intel Corporation
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- System with cache-coherent memory and server-linking switch1 Oct 2026US 2026/0300204 A1Samsung Electronics Co., Ltd.
- Memory system24 Sep 2026US 2026/0288630 A1
Most cited
By later US patents
- Virtual machine monitors for scalable multiprocessors605US 6,075,938 AThe Board of Trustees of the Leland Stanford Junior University · 2000
- System and method for mapping file block numbers to logical block addresses521US 7,437,530 B1Network Appliance, Inc. · 2008
- Dynamic selection of memory virtualization techniques506US 7,752,417 B2Oracle America, Inc. · 2010
- Computing in parallel processing environments463US 8,738,860 B1Tilera Corporation · 2014
- DRAM with high bandwidth interface that uses packets and arbitration313US 5,778,419 AMicroUnity Systems Engineering, Inc. · 1998