Computing in parallel processing environments

A method for configuring a computing system for executing instructions, the method comprising:

• configuring a plurality of single-step engines, at least two single-step engines being associated with different respective protection levels, with a first single-step engine associated with a first protection level being configured to single-step instructions at the first protection level or lower and not at higher protection levels;
• and
• in response to an instruction associated with the first single-step engine being prepared for execution, triggering a corresponding single-step interrupt.

A method for processing packets in a multicore computing system that includes a plurality of cores, the method comprising:

• configuring a first set of one or more of the plurality of cores to execute a program associated with data being communicated to or from the computing system in packets;
• configuring a second set of multiple of the plurality of cores to process packets, with different packets distributed to different cores in the second set for processing based on characteristics of the packets including at least one of source, destination, and protocol, and
• redistributing packets for processing from a first core, selected based at least in part on a quantity of packets being processed by the first core, to a second core, at a time that is determined pseudo-randomly.

A computing system, comprising:

• a plurality of cores, with multiple ones of the plurality of cores each including at least one power supply interface configured to receive a power supply voltage, with a first power supply voltage level enabling at least a first domain of the core when the first power supply voltage is applied to the power supply interface, and a second power supply voltage level disabling the first domain when the second power supply voltage is applied to the power supply interface;
• and
• a plurality of signal isolation transistors, each coupled to a signal conductor path that crosses between domains of respective first and second cores, the signal isolation transistors configured to switch on, to ground the signal path, in response to the first domain being disabled by a corresponding power supply interface, and configured to switch off in response to the first domain being enabled by the corresponding power supply interface.