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US 12,743,378 B2Granted
Address range based memory hints for prefetcher, cache and memory controller
AssigneeGoogle Inc.
InventorsXinliang David Li, Tipp James Moseley, Christopher Thomas Kennelly
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Abstract
The disclosed technology may comprise a mechanism that provides address range based memory hints, based on software memory access patterns. The mechanism includes an interface that can be in the form of a new instruction (“mem_range_hint”) that includes as operands (i) the start of the virtual address (“start_vaddr”), (ii) memory region size (“size”), and (iii) a hint (“hint”) associated with the memory access pattern.
Claims20
A method for processing data in a processing element, comprising:
- determining a starting virtual address and memory access region, the starting virtual address and memory access region defining a memory access range associated with a memory access pattern of a workload being processed by the processing element;
- determining a plurality of memory address hints associated with a memory address range associated with the memory access pattern, the plurality of memory address hints being represented as a bitmask and including a priority hint indicating a scheduling priority of data associated with a portion of the memory access region and a code hint indicating a reused code associated with processing the workload;
- and
- populating one or more memory caches used in processing the data based on one or more of the plurality of memory address hints,
- wherein determining the starting virtual address and memory access region and determining the plurality of memory address hints are performed using an interface between software associated with the workload and the one or more memory caches.
2 more elements
A computing device, comprising:
- a plurality of cache memories, comprising a first level cache, a second level cache and a third level cache arranged such that the second level cache provides first level data to the first level cache and the third level cache provides second level data to the second level cache;
- a prefetch engine having a first input and a second input, the first input coupled to a first output of the second level cache to receive demand misses from the second level cache and the second input configured to receive demand accesses from a level request queue;
- and
- a memory range hint table coupled to the prefetch engine, the range hint table having a plurality of memory address hints associated with a memory address range, the plurality of memory address hints being determined based on a starting memory address and a size value associated with a memory access region that are used to specify a memory access range associated with a memory access pattern of a workload being processed by the processing element, and
- wherein the prefetch engine populates a prefetch queue based on one or more of the plurality of memory address hints.
2 more elements
Dependencies are inferred from the claim text.