Multi-core processor-based system implementing directed page table entry invalidation

A method in a processor-based system comprising a plurality of processor cores (cores) communicatively coupled to each other and configured to couple to a memory system, the method comprising:

• storing page table entries of a virtual machine (VM) in a core translation look-aside buffer (TLB) of each core of the plurality of cores;
• allocating each core of the plurality of cores to one or more of a plurality of sets of cores, comprising a first set of cores;
• and
• in a first core of the plurality of cores:
• obtaining first information that identifies cores in the first set of cores and indicates that at least one core in the first set of cores is assigned to execute instructions of a first VM;
• and
• sending a first message directed to the first set of cores to invalidate copies of a first page table entry of the first VM stored in the core TLBs of the first set of cores.

A non-transitory computer-readable medium comprising instructions which, when executed in a processor-based system comprising a plurality of processor cores (cores) communicatively coupled to each other and configured to couple to a memory system, control the processor-based system to:

• store page table entries of a virtual machine (VM) in a core translation look-aside buffer (TLB) of each core of the plurality of cores;
• allocate each core of the plurality of cores to one or more of a plurality of sets of cores, comprising a first set of cores;
• and
• in a first core of the plurality of cores:
• obtain first information identifying cores in the first set of cores and indicating that at least one core in the first set of cores is assigned to execute instructions of a first VM;
• and
• send a first message directed to the first set of cores to invalidate copies of a first page table entry of the first VM stored in the core TLBs of the first set of cores.