G06F 12/1054
The data cache being concurrently physically addressed
Official title: {the data cache being concurrently physically addressed}
G06F12/1054 (The data cache being concurrently physically addressed) appears on 435 US grants and 324 published applications in this corpus.
Search patents in G06F- Granted patents
- 435
- Published applications
- 324
- Assignees
- 128
- Inventors
- 884
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 2 | 0 |
| 1984 | 2 | 0 |
| 1985 | 2 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 8 | 0 |
| 1991 | 5 | 0 |
| 1992 | 4 | 0 |
| 1993 | 8 | 0 |
| 1994 | 1 | 0 |
| 1995 | 15 | 0 |
| 1996 | 7 | 0 |
| 1997 | 2 | 0 |
| 1998 | 10 | 0 |
| 1999 | 17 | 0 |
| 2000 | 17 | 0 |
| 2001 | 10 | 2 |
| 2002 | 15 | 3 |
| 2003 | 9 | 12 |
| 2004 | 5 | 6 |
| 2005 | 4 | 7 |
| 2006 | 8 | 10 |
| 2007 | 5 | 8 |
| 2008 | 7 | 10 |
| 2009 | 4 | 4 |
| 2010 | 8 | 8 |
| 2011 | 13 | 3 |
| 2012 | 7 | 5 |
| 2013 | 5 | 8 |
| 2014 | 6 | 8 |
| 2015 | 13 | 17 |
| 2016 | 15 | 18 |
| 2017 | 13 | 5 |
| 2018 | 8 | 20 |
| 2019 | 18 | 40 |
| 2020 | 23 | 21 |
| 2021 | 22 | 25 |
| 2022 | 26 | 25 |
| 2023 | 32 | 30 |
| 2024 | 25 | 10 |
| 2025 | 18 | 13 |
| 2026 | 7 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Disaggregated hypervisor25 Aug 2026US 12,717,711 B1NVIDIA Corporation
- Address translation prefetching for input/output devices2 Jun 2026US 12,645,604 B2Microsoft Technology Licensing, LLC
- Virtual partitioning a processor-in-memory (“PIM”)28 Apr 2026US 12,613,808 B2Advanced Micro Devices, Inc.
- Systems and methods for transforming large data into a smaller representation and for re-transforming the smaller representation back to the original large data7 Apr 2026US 12,596,655 B2
- DRAM layout for logical-to-physical (L2P) address indirection table (AIT)31 Mar 2026US 12,591,521 B2SK Hynix NAND Product Solutions Corp.
- Address translation prefetching for input/output devices10 Sep 2026US 2026/0267807 A1Microsoft Technology Licensing, LLC
- System and method for uniform memory access in a network having a plurality of node6 Aug 2026US 2026/0228131 A1Netlist, Inc.
- Dram layout for logical-to-physical (l2p) address indirection table (ait)6 Aug 2026US 2026/0228134 A1SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Apparatus And Method For Predicting Page Addresses To Support Increaded Data Cache Capacity11 Jun 2026US 2026/0161560 A1Intel Corporation
- Physical address determining method and apparatus, computing device, and storage medium21 May 2026US 2026/0140885 A1Huawei Technologies Co., Ltd.
Most cited
By later US patents
- Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures215US 5,854,913 AInternational Business Machines Corporation · 1998
- Computer system with private and shared partitions in cache183US 5,875,464 AInternational Business Machines Corporation · 1999
- Translation buffer for virtual machines with address space match182US 5,319,760 ADigital Equipment Corporation · 1994
- Integrated processing and L2 DRAM cache127US 5,895,487 AInternational Business Machines Corporation · 1999
- Processor with an addressable address translation buffer operative in associative and non-associative modes125US 5,835,963 AHitachi, Ltd. · 1998