System and method for uniform memory access in a network having a plurality of node

A node in a network including a plurality of nodes, comprising:

• a processing unit and a memory unit, the memory unit including a first interface to interface with the processing unit and a second interface to interface with one or more memory units in one or more other nodes of the plurality of nodes;
• and
• wherein the memory unit includes a node control device configurable to:
• receive a memory access request from the processing unit via the first interface;
• in response to the memory access request including a first address in a local unified memory access (UMA) address space accessible by applications running on the processing unit, translate the first address to a second address in a global UMA address space, the global UMA address space being mapped to a physical UMA address space including physical address spaces associated with memory units in the plurality of nodes;
• and
• transmit a first request packet via the second interface, the first request packet including the second address or a first target address for a first target node among the plurality of nodes;
• and
• wherein the network further includes memory access paths, each of the memory access paths is between the second interface of one memory unit in one node and the second interface of another memory unit in another node, and none of the memory access paths go through any of the processing unit in any of the plurality of nodes.