DRAM layout for logical-to-physical (L2P) address indirection table (AIT)

An electronic device, comprising:

• one or more processors;
• and
• memory storing one or more programs for execution by the one or more processors, the one or more programs including instructions for:
• identifying an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses, each logical address corresponding to a distinct physical address;
• determining that a first physical address is associated with a first word having a first word location in the address block;
• extracting the first word from the first word location in the address block;
• based on the first word location, determining a first bit location in a supplemental word that is distinct from the first word, the first bit location in the supplemental word being determined from the first word location in the address block;
• extracting at least a first bit from the first bit location of the supplemental word;
• and
• generating the first physical address based on the first word and the first bit;
• wherein the address block includes a plurality of non-overlapping portions, and each respective portion of the address block includes a respective word choice configured to provide the supplemental word having bits to be combined with remaining address words in the respective portion of the address block.

A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors, the one or more programs comprising instructions for:

• identifying an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses, each logical address corresponding to a distinct physical address;
• determining that a first physical address is associated with a first word having a first word location in the address block;
• extracting the first word from the first word location in the address block;
• based on the first word location, determining a first bit location in a supplemental word that is distinct from the first word, the first bit location in the supplemental word being determined from the first word location in the address block;
• extracting at least a first bit from the first bit location of the supplemental word;
• and
• generating the first physical address based on the first word and the first bit;
• wherein the address block includes a plurality of non-overlapping portions, and each respective portion of the address block includes a respective word choice configured to provide the supplemental word having bits to be combined with remaining address words in the respective portion of the address block.