Processor with an addressable address translation buffer operative in associative and non-associative modes

A data processor comprising:

• a central processing unit generating addresses in an address space and operable in a privileged mode and a user mode, wherein the central processing unit can execute a set of instructions in the privileged mode, wherein the central processing unit can execute only a subset of the set of instructions in the user mode;
• and
• an address translation unit including an address translation buffer and a controller,
• wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,
• wherein the controller is supplied with data and an address having an association bit from the central processing unit and the controller controls associative writing in response to the central processing unit executing an instruction of the subset of instructions in the user mode,
• wherein the controller enables data to be written to a predetermined bit in an entry designated by an address from the central processing unit if a searched address information in an entry of the address translation buffer corresponds to information in the address from the central processing unit, and the controller inhibits data to be written to the predetermined bit in the entry designated by the address from the central processing unit if the searched address information in the entry of the address translation buffer does not correspond to the information in the address from the central processing unit, when an association bit of an address is in a first state.

A data processor comprising:

• a central processing unit generating addresses in an address space and including a plurality of registers;
• and
• an address translation unit including an address translation buffer and a controller,
• wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,
• wherein the controller is supplied with data stored in a first register of the plurality of registers and is supplied with an address including an association bit stored in a second register of the plurality of registers, wherein the controller controls associative writing in response to the central processing unit executing an instruction, and
• wherein the controller enables data stored in the first register to be written to a predetermined bit in an entry designated by the address stored in the second register if a searched address information in an entry of the address translation buffer corresponds to information in the address stored in the second register, and the controller inhibits data stored in the first register to be written to the predetermined bit in the entry of the address translation buffer if the searched address information in the entry of the address translation buffer does not correspond to the information in the address stored in the second register, when an association bit of an address is in a first state.

A data processor comprising:

• a central processing unit generating addresses in an address space and including a plurality of registers;
• and
• an address translation unit including an address translation buffer and a controller,
• wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,
• wherein the controller is supplied with data stored in a first register of the plurality of registers and is supplied with an address including an association bit stored in a second register of the plurality of registers, wherein the controller controls associative writing in response to the central processing unit executing a MOVE instruction for instructing data transfer, and
• wherein the controller enables the data stored in the first register to be written to a predetermined bit in an entry designated by the address stored in the second register if a searched address information in an entry of the address translation buffer corresponds to information in the address stored in the second register, and the controller inhibits the data stored in the first register to be written to the predetermined bit in the entry if the searched address information in the entry of the address translation buffer does not correspond to the information in the address stored in the second register, when an association bit of an address is in a first state.